Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: Disclosed herein is a modular deck system that utilizes a combination of a movable platform having a plurality of vertical posts with engagement members. Decks, filled with freight, can be placed onto the vertical posts at various heights at different sections of the movable platform using a conveyance vehicle. Further, the height of the vertical posts can be extended using an extension post for securing tall cargo. The decks can also be locked to the vertical posts to prevent dislodgement of the deck during transport of the movable platform.

Abstract: Disclosed herein is a movable platform (MP) for moving freight during cross-dock operations. The MP comprises a mechanical lift brake assembly that can be utilized to deploy a plurality of mechanical lift brakes preventing further movement of the MP. AMP forklift attachment that can be used to convey the MP and to engage or disengage the mechanical lift brake assembly. The MP forklift attachment can be attached to a conveyance vehicle, such as a forklift, or built into an automated guided vehicle.

Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.

Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

Abstract: Network packet tracing may be implemented on packet processors or other devices that perform packet processing. As network packets are received, a determination may be made as to whether tracing is enabled for the network packets. For those network packets with tracing enabled, trace information may be generated and the network packets modified to include the trace information such that forwarding decisions for the network packets ignore the trace information. Trace information indicate a packet processor as a location in a route traversed by the network packets and may include ingress and egress timestamps. Forwarding decisions may then be made and the network packets sent according to the forwarding decisions. Tracing may be enabled or disabled by packet processors for individual network packets. Trace information may also be truncated at a packet processor.

Abstract: Disclosed herein is a modular deck system that utilizes a combination of a movable platform having a plurality of vertical posts with engagement members. Decks, filled with freight, can be placed onto the vertical posts at various heights at different sections of the movable platform using a conveyance vehicle. Further, the height of the vertical posts can be extended using an extension post for securing tall cargo. The decks can also be locked to the vertical posts to prevent dislodgement of the deck during transport of the movable platform.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

Abstract: Disclosed herein are techniques for migrating data from a source memory range to a destination memory while data is being written into the source memory range. An apparatus includes a control logic configured to receive a request for data migration and initiate the data migration using a direct memory access (DMA) controller, while the source memory range continues to accept write operations. The apparatus also includes a tracking logic coupled to the control logic and configured to track write operations performed to the source memory range while data is being copied from the source memory range to the destination memory. The control logic is further configured to initiate copying data associated with the tracked write operations to the destination memory.

Abstract: A head mounted display (HMD) device may include a housing coupled to a frame, and a display device disposed in the housing. A first lens may be disposed along a first optical axis in the housing, and a second lens may be disposed along a second optical axis in the housing. A divider may be positioned between the first lens and the second lens, with a front end portion of the divider positioned adjacent to the display device. The divider may include display capability so that images displayed on the display device may extend onto the divider. The divider may emit diffused light having chrominance and/or luminance levels corresponding to images displayed on the display device. The divider may reflect diffused light from images displayed on the display device. The divider may transmit diffused light from images displayed on the display device.

Abstract: The present invention relates to compounds which bind to Beta Trans-ducin repeat-containing protein (?TrCP), and modulate the activity of ?TrCP. In particular, the invention relates to compounds which demonstrate optimised binding to PTrCP. The invention also relates to pharmaceutical compositions comprising such compounds and the use of such compounds as medicaments, specifically for the treatment of disorders associated with aberrant protein degradation, such as cancer. The preferred binding inhibitors are peptides derived from the motive DSGXXS, e.g. DEGFWE, DDGFWD and Succinyl-EGFWE.

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

Abstract: An electronics adapter and method are disclosed herein. The electronics adapter can include a plurality of interface ports, with each interface port from the device coupled to a processor from a plurality of processors, and a controller communicatively coupled to the interface ports. The controller may be configured to determine a function or transaction attributes, which are serviced by instructions executed by one of the processors. The controller may be further configured to determine at least one interface port on the adapter to transmit the transaction based on the function or the attributes using an updatable mapping between the function or the attributes and the interface port, and transmit a request for the transaction using the interface port for processing of the transaction by the processor coupled to the interface port.

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

Abstract: Implementations of discovery functionalities in accordance with the present invention are characterized by being exceptionally minimalistic. A primary reason and benefit for such minimalistic implementations relate to these discovery functionalities being implemented via a management processor and associated resources of a system on a chip (SoC) unit as opposed to them being implemented on data processing components of a cluster of nodes (i.e., central processing core components). By focusing on such a minimalist implementation, embodiments of the present invention allow discovery functionalities to be implemented on a relatively low-cost low-power management processor coupled to processing cores that provide for data serving functionality in the cluster of nodes.

Abstract: Disclosed herein is a movable platform (MP) for moving freight during cross-dock operations. The MP comprises a mechanical actuation assembly used to deploy a plurality of roller assemblies used for moving the MP. Also disclosed is an actuating attachment used to deploy the mechanical actuation assembly of the MP. The actuating attachment can be attached to a conveyance vehicle, such as a forklift, or built in to an automated guided vehicle.

Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.