Abstract: A server apparatus comprises a plurality of server on a chip (SoC) nodes interconnected to each other through a node interconnect fabric. Each one of the SoC nodes has respective memory resources integral therewith. Each one of the SoC nodes has information computing resources accessible by one or more data processing systems. Each one of the SoC nodes configured with memory access functionality enabling allocation of at least a portion of said memory resources thereof to one or more other ones of the SoC nodes and enabling allocation of at least a portion of said memory resources of one or more other ones of the SoC nodes thereto based on a workload thereof.

Abstract: Disclosed herein is a movable platform (MP) for moving freight during cross-dock operations. The MP comprises a mechanical actuation assembly used to deploy a plurality of roller assemblies used for moving the MP. Also disclosed is an actuating attachment used to deploy the mechanical actuation assembly of the MP. The actuating attachment can be attached to a conveyance vehicle, such as a forklift, or built in to an automated guided vehicle.

Abstract: Server computers may include one or more input/output (I/O) adapter devices for communicating with a network and/or direct-attached device. The I/O adapter device may implement processes to manage write requests in a general and flexible manner. The I/O adapter device may also implement processes to manage write requests in a fast an efficient—that is, low latency—manner. Low latency write requests processes may include determining that a write packet for a write request can be processed without additional assistance from a processor, once a processor has initiated a memory access request to fetch write data and also generated protocol information for transmitting the write packet. The I/O adapter device may then process and transmit the write packet through an offload pipeline, without interrupting a processor.

Abstract: A system that provides virtualized computing resources to clients or subscribers may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware devices in software. In response to receiving a transaction layer packet that includes a transaction directed to an emulated device, the endpoint device may process the transaction, which may include emulating the target emulated device. The endpoint device may include multiple PCIe controllers and may expose multiple PCIe endpoints to a host computing system. For example, each PCIe controller may be physically coupled to one of multiple host processor sockets or host server SOCs on the host computing system, each of which exposes its own root complex. Traffic received by the PCIe controllers may be merged on the endpoint device for subsequent processing. Traffic originating at one host processor socket may be steered to the PCIe controller to which it is directly attached.

Abstract: Techniques are described for logging communication traffic associated with one or more devices. For example, a system bus or other interface to a device may be monitored for traffic data elements. The traffic data elements may include, for example, transaction layer packets (TLPs) for communication across a PCI Express interface, or Ethernet packets for communication over a network. The traffic data elements can be processed by a classifier module and accordingly routed to one of a plurality of circular buffers. The circular buffers may maintain state (e.g., a head pointer and a tail pointer) that identify traffic data elements that are pending and those that are completed. Thus, the circular buffers can be inspected (such as after a crash) to determine recent activity.

Abstract: Disclosed herein is a movable platform (MP) for moving freight during cross-dock operations. The MP comprises a mechanical lift brake assembly that can be utilized to deploy a plurality of mechanical lift brakes preventing further movement of the MP. AMP forklift attachment that can be used to convey the MP and to engage or disengage the mechanical lift brake assembly. The MP forklift attachment can be attached to a conveyance vehicle, such as a forklift, or built into an automated guided vehicle.

Abstract: A head mounted display (HMD) includes a first display portion included in the HMD, the first display portion having a first pixel density, a second display portion included in the HMD, the second display portion having the first pixel density, a third display portion attached to the HMD, the third display portion having a second pixel density, and at least one image combiner configured to combine two images by reflecting an image projected by the first display portion and the second display portion and allowing an image projected by the third display portion to pass through the at least one image combiner.

Abstract: A probe is provided comprising a label and a binding moiety, Deliver First Probe wherein the binding moiety is adapted to bind to gram-negative bacteria, and to Target Area to substantially not bind to animal cells or gram-positive bacteria. A method of detecting the presence of bacteria in a target area is also provided, which allows the detection of bacteria generally, and the determination of whether that bacteria is gram negative or gram positive.

Abstract: A system that provides virtualized computing resources may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware in software. The endpoint device may include host interface circuitry that implements pointer registers and control and status registers for each of multiple transaction ring buffers instantiated in memory on the device. In response to receiving a transaction layer packet that includes a transaction, packet steering circuitry may push the transaction into one of the buffers, dependent on the transaction type, a routing identifier for an emulated device to which it is directed, its traffic class or other criteria. The transaction may be processed in software, emulating the hardware device. The host interface circuitry may generate response completion packets for configuration requests and non-posted transactions, and may return them according to PCIe ordering rules, regardless of the order in which they were processed on the endpoint device.

Abstract: Disclosed herein is a movable platform (MP) for moving freight during cross-dock operations. The MP comprises a mechanical actuation assembly used to deploy a plurality of roller assemblies used for moving the MP. Also disclosed is an actuating attachment used to deploy the mechanical actuation assembly of the MP. The actuating attachment can be attached to a conveyance vehicle, such as a forklift, or built in to an automated guided vehicle.

Abstract: The present invention provides a movable platform (MP) having a simple construction that is capable of being conveyed by a hydraulically actuated skate system (HASS). The MP is able to accommodate freight placed upon its surface and can be used to fully load a trailer in a single cross-dock move. The HASS can be used to move the MP during cross-dock operations. The HASS comprises a plurality of tines which are received in corresponding support channels in the MP. The tines are used to lift the MP off the ground and rollers on the tines can be used to move the MP. A conveyance vehicle is used to move the HASS and the MP after the tines have been actuated.

Abstract: Disclosed herein is a modular deck system that utilizes a combination of a movable platform having a plurality of vertical posts with engagement members. Decks, filled with freight, can be placed onto the vertical posts at various heights at different sections of the movable platform using a conveyance vehicle. Further, the height of the vertical posts can be extended using an extension post for securing tall cargo. The decks can also be locked to the vertical posts to prevent dislodgement of the deck during transport of the movable platform.

Abstract: A probe is provided comprising a core and a plurality of probe elements; each probe element within the plurality of probe elements extending from the core and comprising a fluorophore and a binding moiety. Methods of use of the probe and kits comprising the probe are also provided.

Abstract: A system that provides virtualized computing resources to clients or subscribers may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware devices in software. In response to receiving a transaction layer packet that includes a transaction directed to an emulated device, the endpoint device may process the transaction, which may include emulating the target emulated device. The endpoint device may include multiple PCIe controllers and may expose multiple PCIe endpoints to a host computing system. For example, each PCIe controller may be physically coupled to one of multiple host processor sockets or host server SOCs on the host computing system, each of which exposes its own root complex. Traffic received by the PCIe controllers may be merged on the endpoint device for subsequent processing. Traffic originating at one host processor socket may be steered to the PCIe controller to which it is directly attached.

Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.

Abstract: In a multi-tenant environment, separate virtual machines can be used for configuring and operating different subsets of programmable integrated circuits, such as a Field Programmable Gate Array (FPGA). The programmable integrated circuits can communicate directly with each other within a subset, but cannot communicate between subsets. Generally, all of the subsets of programmable ICs are within a same host server computer within the multi-tenant environment, and are sandboxed or otherwise isolated from each other so that multiple customers can share the resources of the host server computer without knowledge or interference with other customers.

Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.

Abstract: A multi-tenant environment is described with configurable hardware logic (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. For communicating with the configurable hardware logic, an intermediate host integrated circuit (IC) is positioned between the configurable hardware logic and virtual machines executing on the host server computer. The host IC can include management functionality and mapping functionality to map requests between the configurable hardware logic and the virtual machines. Shared peripherals can be located either on the host IC or the configurable hardware logic. The host IC can apportion resources amongst the different configurable hardware logics to ensure that no one customer can over consume resources.