Patents by Inventor Mark E. Tuttle

Mark E. Tuttle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200126907
    Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.
    Type: Application
    Filed: December 4, 2019
    Publication date: April 23, 2020
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Patent number: 10593568
    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
  • Patent number: 10580710
    Abstract: A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top surface; a die attached over the substrate, wherein the die includes a die bottom surface that connects to the interconnects for electrically coupling the die and the substrate; and a metal enclosure directly contacting and vertically extending between the substrate top surface and the die bottom surface, wherein the metal enclosure peripherally surrounds the interconnects.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Zhou, Bret K. Street, Mark E. Tuttle
  • Patent number: 10529659
    Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Publication number: 20190304860
    Abstract: A semiconductor device assembly including a substrate, a semiconductor device, a stiffener member, and mold compound. The stiffener member is tuned, or configured, to reduce and/or control the shape of warpage of the semiconductor device assembly at an elevated temperature. The stiffener member may be placed on the substrate, on the semiconductor device, and/or on the mold compound. A plurality of stiffener members may be used. The stiffener members may be positioned in a predetermined pattern on a component of the semiconductor device assembly. A stiffener member may be used so that the warpage of a first semiconductor device substantially corresponds to the warpage of a second semiconductor device at an elevated temperature. The stiffener member may be tuned by providing the member with a desired coefficient of thermal expansion (CTE). The desired CTE may be based on the individual CTEs of the components of a semiconductor device assembly.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Inventors: Chan H. Yoo, Mark E. Tuttle
  • Publication number: 20190273029
    Abstract: A semiconductor device includes a substrate; a die attached to the substrate; an encapsulation covering the substrate and the die, wherein the die is embedded within the encapsulation; and a heating element embedded within the encapsulation, wherein the heating element is configured to provide thermal energy to the die.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 5, 2019
    Inventor: Mark E. Tuttle
  • Publication number: 20190274232
    Abstract: A semiconductor device includes a substrate; a first functional circuit attached to the substrate; a first thermal circuit attached to the substrate, configured to utilize cryogenic liquid to cool the first functional circuit; a second functional circuit attached to the substrate; and a second thermal circuit attached to the substrate, configured to cool the second functional circuit without using the cryogenic liquid.
    Type: Application
    Filed: March 2, 2018
    Publication date: September 5, 2019
    Inventor: Mark E. Tuttle
  • Patent number: 10396003
    Abstract: A semiconductor device assembly including a substrate, a semiconductor device, a stiffener member, and mold compound. The stiffener member is tuned, or configured, to reduce and/or control the shape of warpage of the semiconductor device assembly at an elevated temperature. The stiffener member may be placed on the substrate, on the semiconductor device, and/or on the mold compound. A plurality of stiffener members may be used. The stiffener members may be positioned in a predetermined pattern on a component of the semiconductor device assembly. A stiffener member may be used so that the warpage of a first semiconductor device substantially corresponds to the warpage of a second semiconductor device at an elevated temperature. The stiffener member may be tuned by providing the member with a desired coefficient of thermal expansion (CTE). The desired CTE may be based on the individual CTEs of the components of a semiconductor device assembly.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Mark E. Tuttle
  • Publication number: 20190247943
    Abstract: A solder removal apparatus is provided. The solder removal apparatus comprises a plurality of solder-interfacing protrusions extending from a body by a length. Each of the plurality of solder-interfacing protrusions is configured to remove a corresponding one of a plurality of solder features from a semiconductor device, where each of the plurality of solder features has a height and an amount of solder material.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventor: Mark E. Tuttle
  • Publication number: 20190237438
    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.
    Type: Application
    Filed: April 9, 2019
    Publication date: August 1, 2019
    Inventors: Chan H. Yoo, Mark E. Tuttle
  • Publication number: 20190198443
    Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.
    Type: Application
    Filed: November 7, 2018
    Publication date: June 27, 2019
    Inventors: Eiichi Nakano, Mark E. Tuttle
  • Publication number: 20190170811
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.
    Type: Application
    Filed: February 6, 2019
    Publication date: June 6, 2019
    Inventor: Mark E. Tuttle
  • Patent number: 10307850
    Abstract: A solder removal apparatus is provided. The solder removal apparatus comprises a plurality of solder-interfacing protrusions extending from a body by a length. Each of the plurality of solder-interfacing protrusions is configured to remove a corresponding one of a plurality of solder features from a semiconductor device, where each of the plurality of solder features has a height and an amount of solder material.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 4, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Patent number: 10304805
    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Mark E. Tuttle
  • Publication number: 20190115270
    Abstract: A semiconductor device assembly including a substrate, a semiconductor device, a stiffener member, and mold compound. The stiffener member is tuned, or configured, to reduce and/or control the shape of warpage of the semiconductor device assembly at an elevated temperature. The stiffener member may be placed on the substrate, on the semiconductor device, and/or on the mold compound. A plurality of stiffener members may be used. The stiffener members may be positioned in a predetermined pattern on a component of the semiconductor device assembly. A stiffener member may be used so that the warpage of a first semiconductor device substantially corresponds to the warpage of a second semiconductor device at an elevated temperature. The stiffener member may be tuned by providing the member with a desired coefficient of thermal expansion (CTE). The desired CTE may be based on the individual CTEs of the components of a semiconductor device assembly.
    Type: Application
    Filed: October 18, 2017
    Publication date: April 18, 2019
    Inventors: Chan H. Yoo, Mark E. Tuttle
  • Patent number: 10261123
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Mark E. Tuttle
  • Publication number: 20190064257
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventor: Mark E. Tuttle
  • Publication number: 20190067038
    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
    Type: Application
    Filed: September 6, 2018
    Publication date: February 28, 2019
    Inventors: Chan H. Yoo, John F. Kaeding, Ashok Pachamuthu, Mark E. Tuttle
  • Publication number: 20190061034
    Abstract: A solder removal apparatus is provided. The solder removal apparatus comprises a plurality of solder-interfacing protrusions extending from a body by a length. Each of the plurality of solder-interfacing protrusions is configured to remove a corresponding one of a plurality of solder features from a semiconductor device, where each of the plurality of solder features has a height and an amount of solder material.
    Type: Application
    Filed: August 24, 2017
    Publication date: February 28, 2019
    Inventor: Mark E. Tuttle
  • Publication number: 20190067137
    Abstract: A semiconductor device includes a substrate including a substrate top surface; interconnects connected to the substrate and extending above the substrate top surface; a die attached over the substrate, wherein the die includes a die bottom surface that connects to the interconnects for electrically coupling the die and the substrate; and a metal enclosure directly contacting and vertically extending between the substrate top surface and the die bottom surface, wherein the metal enclosure peripherally surrounds the interconnects.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Wei Zhou, Bret K. Street, Mark E. Tuttle