Abstract: A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem with a clock signal generator. The distribution die is electrically connected through an interface technology, such as microbumps, to route the clock signals to the functional circuits on a separate functional die. Alternatively, the distribution die could be electrically connected to more than one die at a time, using vias through the distribution die to route the clock signals to the different die. This separate distribution die reduces the coupling between lines and also helps to prevent signal skew as the signal moves through the distribution network.

Abstract: A stacked structure includes a first die coupled to a first substrate and having a first conductive structure formed through the first die. A second die is mounted over the first die. The second die is coupled to the first substrate by the first conductive structure. At least one first support structure formed from a second substrate is provided over the first substrate, adjacent to at least one of the first die and the second die. A top surface of the first support structure is substantially coplanar with a top surface of at least one of the first and second dies adjacent to the first support structure. The stacked structure further includes a heat spreader mounted over the second die.

Abstract: An isolation structure for electromagnetic interference includes a semiconductor substrate, a first integrated circuit in the semiconductor substrate, a second integrated circuit in the semiconductor substrate, and an isolation structure in a direct path between the first and the second integrated circuits, wherein the isolation structure comprises a through-silicon via.

Abstract: An interposer for converting pitches includes an interconnect structure over the semiconductor substrate, an active circuit formed on the semiconductor substrate, wherein the active circuit is electrically connected to the interconnect structure, a first plurality of pads with a first pitch over the interconnect structure, a second plurality of pads underlying the semiconductor substrate, and a plurality of through-substrate vias in the semiconductor substrate, wherein the first and the second plurality of pads are interconnected through the plurality of through-substrate vias.