Abstract: An image data decompression apparatus for decoding blocks of motion compensated non-intra coded data uses a memory (14) storing reference picture data. A decoding processor (12) decodes a current block of a generated picture using lines of previously decoded image data from the memory (14) that are selected in dependence upon a motion vector (V1) for the current block. In order to improve access efficiency to the memory (14) the decoding processor (12) concatenates fetches into bursts for different sections of lines of previously decoded data that lie within a predetermined range within the memory addresses of the memory (14).

Abstract: A system and method for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip.

Abstract: A system and method for accelerated handling of masked store operations in a processor or processor-based system/chip are described. A set of instructions that support a store operation under a per-byte predicate mask is provided. The invention accelerates the handling of small transfers at arbitrary alignments, such as those used by xDSL modems to deal with ATM cells or Reed Solomon codewords.

Abstract: A method is used that substantially simultaneously trellis encodes data to be modulated onto multiple tones. The embodiments of the present invention comprise the steps of: (a) using a first input operand comprising state bits for a first trellis stage; (b) using a second input operand comprising a plurality of input data bits; and (c) generating an output comprising output data bits and output state bits from a first or later trellis stage.

Abstract: A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit configured to extract a plurality of bit fields from a source reservoir and to populate a plurality of destination lanes in response to a single instruction. In addition, the execution unit is configured to write supplied fill data into the source reservoir if the number of bits in the source reservoir is less than a predetermined number. In addition or alternatively, the system may include at least one execution unit configured to combine a plurality of bit fields from a plurality of source lanes into a continuous bit stream in response to a single instruction executable by the processor.

Abstract: A system and method for accelerated performance of quadrature amplitude modulation (QAM) is provided. The system includes multiple general purpose registers and multiple execution units configured to decode a set of QAM tones in parallel or an individual QAM tone in response to a single instruction executable by the processor. Each of the plurality of execution units is configured to decode one of the set of QAM tones according to a constellation size associated with the one of the set of QAM tones. The QAM decoding method includes reading a constellation size value for each of a set of received input tones. For each tone in the set of input tones, an ideal point in a QAM constellation of the associated constellation size closest to the X and Y coordinates of the tone is determined. The data values of the ideal points are then stored in a destination register.

Abstract: A method is used that substantially simultaneously trellis encodes data to be modulated onto multiple tones. The embodiments of the present invention comprise the steps of: (a) using a first input operand comprising state bits for a first trellis stage; (b) using a second input operand comprising a plurality of input data bits; and (c) generating an output comprising output data bits and output state bits from a first or later trellis stage.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12, 14, 16 and corresponding stages of intermediate data 18,20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude that the symbol would contain after the subsequent processing in the analogue front end 146 is modelled and compared with a threshold. If the modelled peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated. The symbols stored in the buffer are output through the analogue front end 146.

Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12,14,16 and corresponding stages of intermediate data 18,20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude that the symbol would contain after the subsequent processing in the analogue front end 146 is modelled and compared with a threshold. If the modelled peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated. The symbols stored in the buffer are output through the analogue front end 146.

Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12, 14, 16 and corresponding stages of intermediate data 18, 20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude contained in the symbol is detected 28 and compared with a threshold. If the peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated.

Abstract: A multi-tone modem processes an input data stream 10 and uses an inverse Fourier transform 24 to produce a stream of multi-tone symbols 26 fed to an analogue front end 146. A model 32 models the subsequent processing in the analogue front end 146 and outputs a control signal 184 that controls the analogue front end 146 accordingly.

Abstract: Methods and systems for executing SIMD instructions that efficiently implement new SIMD instructions and conventional existing SIMD MAC-type instructions, while avoiding replication of functions in order to keep the size of the logic circuit size to as low a level as can reasonably be achieved. An instruction unit executes Single Instruction Multiple Data instructions, including instructions acting on operands representing complex numbers. The instruction unit includes functional blocks that are commonly utilized to execute a plurality of the instructions, wherein the plurality of instructions utilize various individual functional blocks in various combinations with one another. The plurality of instructions is optionally executed in a pipeline fashion.

Abstract: An FFT conversion instruction based on a single instruction multiple data (“SIMD”) technique is executed to reduce the number of cycles for software to perform conversion processing used in an FFT computation. In an embodiment, the FFT conversion instruction implements two instances of a conversion operation, i.e., 2-way SIMD, over two sets of complex points at once. A control register or variant opcode controls an inverse flag to control the behavior of the conversion process. In an embodiment, the control register contains a control bit to select between forward and inverse FFT context.

Abstract: A method is used that substantially simultaneously trellis encodes data to be modulated onto multiple tones. The embodiments of the present invention comprise the steps of: (a) using a first input operand comprising state bits for a first trellis stage; (b) using a second input operand comprising a plurality of input data bits; and (c) generating an output comprising output data bits and output state bits from a first or later trellis stage.

Abstract: A method, apparatus and processing instruction for performing DMT encoding substantially simultaneously on one tone or multiple tones comprises the steps of: (a) using a first input operand comprising one or more bit-group data values, each to be encoded for one or more tones; (b) using a second input operand comprising one or more bit-group size values corresponding to the bit-group data values in the first input operand; and (c) generating an output comprising a result of encoding the bit-group data value or values from the first input operand by mapping each of the bit-group data values from the first input operand onto a location in a constellation as determined by the corresponding bit-group size value or values from the second input operand.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: A method and apparatus are disclosed for efficiently de-scrambling one or more bytes of data according to DSL standards on a processor. This is achieved by providing an instruction for de-scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to de-scramble data with a single instruction thus allowing for more efficient and faster de-scrambling operations for subsequent processing.

Abstract: A method for multiplying, at an execution unit of a processor, two complex numbers in which all four scalar multiplications, concomitant to multiplying two complex numbers, can be performed in parallel. A real part of a first complex number is multiplied at the execution unit by a real part of a second complex number to produce a first part of a real part of a third complex number. An imaginary part of the first complex number is multiplied at the execution unit by an imaginary part of the second complex number to produce a second part of the real part of the third complex number. A first arithmetic function is performed at the execution unit between the first part of the real part of the third complex number and the second part of the real part of the third complex number. The imaginary part of the first complex number is multiplied at the execution unit by the real part of the second complex number to produce a first part of an imaginary part of the third complex number.

Abstract: A method and apparatus are disclosed for efficiently bit-reversing and scrambling one or more bytes of payload data according to DSL standards on a processor. In one embodiment, this is achieved by providing an instruction for bit reversing and scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to bit reverse and scramble data with a single instruction thus allowing for more efficient and faster scrambling operations for subsequent modulation and transmission.