Abstract: A method for multiplying, at an execution unit of a processor, two complex numbers in which a real part and an imaginary part of a product of the multiplying can be stored in a same register of the processor. First data is conveyed along at least a first interconnect of the processor. The first data has a first operand. The first operand represents a first complex number. Second data is conveyed along at least a second interconnect of the processor. The second data has a second operand. The second operand represents a second complex number. The first operand is multiplied at the execution unit by the second operand to produce a first result. The first result represents a third complex number. Third data is stored at a first register of the processor. The third data has the first result. The first result has at least the product of the multiplying.

Abstract: In an Asynchronous Transfer Mode cell, a method and apparatus are disclosed for producing a cell header having bytes with bits in reverse order. Address and control data bytes are received, and a value for a reverse bit Header Error Control byte is generated from the address and control data bytes. Additionally, the order of bits within each address and control data byte is reversed. The produced cell header comprises the reverse bit Header Error Control byte and the address and control data bytes with each address and control data byte having its bits in reversed order. In one embodiment, the present invention provides a processor instruction for producing the cell header having bytes with bits in reverse order. The instruction receives as input address and control data bytes. The instruction then computes a Header Error Control byte and formats the Header Error Control byte in reverse bit order for subsequent processing within the modem.

Abstract: A method and apparatus are disclosed for efficiently scrambling one or more bytes of data according to DSL standards on a processor. This is achieved by providing an instruction for scrambling one or more bytes of data according to the DSL standards. Accordingly, the invention advantageously provides a processor with the ability to scramble data with a single instruction thus allowing for more efficient and faster scrambling operations for subsequent modulation and transmission.

Abstract: An FFT butterfly instruction based on single instruction multiple data (“SIMD”) technique is executed to reduce the number of cycles for software to perform FFT butterfly operations. The FFT butterfly instruction can implement one or more instances of the FFT butterfly operation (e.g., non-SIMD, 2-way SIMD, 4-way SIMD, etc.), at once, each instance operating over a set of complex values. A control register or variant opcode controls the behavior of the FFT butterfly operation. The contents of the control register or the variant opcode can be altered to configure the butterfly behavior to suit specific circumstances. The FFT butterfly instruction can be used in the software on a processor in a chip-set implementing the central-office modem end of a DSL link. The FFT butterfly instruction can also be used in other contexts where an FFT function is performed (and/or where an FFT butterfly operation is used) including systems that do not implement DSL or DMT.

Abstract: A method and apparatus are disclosed for efficiently de-scrambling and bit-order-reversing one or more bytes of data according to DSL standards on a processor. In a preferred embodiment, this is achieved by providing an instruction for de-scrambling and bit-order-reversing one or more bytes of data according to DSL standards. Accordingly, the invention advantageously provides a processor with the ability to de-scramble and bit-order-reverse data with a single instruction thus allowing for more efficient and faster de-scrambling operations for subsequent processing.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: An image data decoding system (2) is described in which a stream of compressed image data (1) corresponding to a plurality of image channels (ChA, ChB, ChC) each comprising intra-coded pictures (I) and inter-coded pictures (B, P) is received. A selected channel within the plurality of channels is fully decoded to produce display driving data. At least one non-selected channel is at least partially processed by the system even though it is not being displayed such that if a switch is made to that non-selected channel then display driving data for that newly selected channel can be produced without having to wait for the next intra-coded picture (I) to be received. The partial processing may take the form of merely buffering the compressed data for the non-selected channel. Alternatively, reference pictures or all pictures for the non-selected channel may be either fully decoded, or partially decoded to produce spatially sub-sampled versions of the pictures of the non-selected channels.

Abstract: An image data decompression apparatus for decoding blocks of motion compensated non-intra coded data uses a memory (14) storing reference picture data. A decoding processor (12) decodes a current block of a generated picture using lines of previously decoded image data from the memory (14) that are selected in dependence upon a motion vector (V1) for the current block In order to improve access efficiency to the memory (14) the decoding processor (12) concatenates fetches into bursts for different sections of lines of previously decoded data that lie within a predetermined range within the memory addresses of the memory (14).

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: An image data decoding system (2) is described in which a stream of compressed image data (1) corresponding to a plurality of image channels (ChA, ChB, ChC) each comprising intra-coded pictures (I) and inter-coded pictures (B, P) is received. A selected channel within the plurality of channels is fully decoded to produce display driving data. At least one non-selected channel is at least partially processed by the system even though it is not being displayed such that if a switch is made to that non-selected channel then display driving data for that newly selected channel can be produced without having to wait for the next intra-coded picture (I) to be received. The partial processing may take the form of merely buffering the compressed data for the non-selected channel. Alternatively, reference pictures or all pictures for the non-selected channel may be either fully decoded, or partially decoded to produce spatially sub-sampled versions of the pictures of the non-selected channels.

Abstract: An image data decompression apparatus for decoding blocks of motion compensated non-intra coded data uses a memory (14) storing reference picture data. A decoding processor (12) decodes a current block of a generated picture using lines of previously decoded image data from the memory (14) that are selected in dependence upon a motion vector (V1) for the current block. In order to improve access efficiency to the memory (14) the decoding processor (12) concatenates fetches into bursts for different sections of lines of previously decoded data that lie within a predetermined range within the memory addresses of the memory (14).

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: An image data decoding system (2) is described in which a stream of compressed image data (1) corresponding to a plurality of image channels (ChA, ChB, ChC) each comprising intra-coded pictures (I) and inter-coded pictures (B, P) is received. A selected channel within the plurality of channels is fully decoded to produce display driving data. At least one non-selected channel is at least partially processed by the system even though it is not being displayed such that if a switch is made to that non-selected channel then display driving data for that newly selected channel can be produced without having to wait for the next intra-coded picture (I) to be received. The partial processing may take the form of merely buffering the compressed data for the non-selected channel. Alternatively, reference pictures or all pictures for the non-selected channel may be either fully decoded, or partially decoded to produce spatially sub-sampled versions of the pictures of the non-selected channels.

Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12,14,16 and corresponding stages of intermediate data 18,20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude that the symbol would contain after the subsequent processing in the analogue front end 146 is modelled and compared with a threshold. If the modelled peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated. The symbols stored in the buffer are output through the analogue front end 146.

Abstract: A multi-tone modem processes an input data stream 10 and uses an inverse Fourier transform 24 to produce a stream of multi-tone symbols 26 fed to an analogue front end 146. A model 32 models the subsequent processing in the analogue front end 146 and outputs a control signal 184 that controls the analogue front end 146 accordingly.

Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12, 14, 16 and corresponding stages of intermediate data 18, 20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude contained in the symbol is detected 28 and compared with a threshold. If the peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated.

Abstract: A digital/analogue communication system is described, where data is generated and received by a processing unit in a digital format and transmitted via a communication path in an analogue format. A DSP unit receives a sequence of multi-bit digital samples at a first sampling rate and generates a plurality of interpolated samples. A bit generation unit receives the multi-bit digital samples and the interpolated samples and generates a sequence of single-bit digital samples at a second sampling rate which is higher than the first sampling rate. A set of single wire communication paths are used to convey the single-bit digital samples to respective digital to analogue converters. The use of single-bit digital samples allows them to be held in a buffer. A buffer controller can be provided to delete single-bit digital samples from the buffer so as to match the sampling times at at least one reference frequency of a received signal with sampling times of a generated signal.