Patents by Inventor Mark V. Pierson

Mark V. Pierson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6173887
    Abstract: A method of making an electrically conductive contact on a substrate by applying a layer of solder paste to a circuitized feature on a substrate and selectively heating and melting the solder paste over the feature to form a solder bump. The excess solder paste is removed. A focused energy heat source such as a laser beam or focused Infrared heats the solder paste. In another embodiment, a reflective mask with apertures may be used to allow focused heating source to selectively melt areas of the solder paste layer applied to a circuitized feature. In yet another embodiment, a reflective mask with apertures filled with solder paste is applied onto a substrate and then heated to cause localized solder melting. The mask and excess solder paste are removed.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: January 16, 2001
    Assignee: International Business Machines Corporation
    Inventors: Donald I. Mead, Mark V. Pierson
  • Patent number: 6142361
    Abstract: A method, and associated structure, for adhesively coupling a chip to an organic chip carrier. The chip is attached to a top surface of the organic chip carrier by interfacing a solder bump between a C4 solder structure on the chip and a pad on a top surface of the chip carrier. The melting temperature of the solder bump is less than the melting temperature of the C4 solder structure. A block of ferrous material is placed on a top surface of the chip. A temporary or permanent stiffener of ferrous material is placed on the top surface of the chip carrier. A permanent magnet is coupled to a bottom surface of the chip carrier. Alternatively, an electromagnetic could be utilized instead of the electromagnet. Due to the permanent magnet or the electromagnet, a magnetic force on the stiffener is directed toward the magnet and substantially flattens the first surface of the chip carrier.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: November 7, 2000
    Assignee: International Business Machines Corporation
    Inventors: Francis J. Downes, Jr., Robert M. Japp, Mark V. Pierson
  • Patent number: 6129804
    Abstract: A system for aligning and attaching together a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate loading station where a coverplate that the tiles are to be attached to is arranged on a coverplate support. A coverplate bonding material dispensing station where a bonding material for bonding the tiles to the coverplate is applied to a surface of the coverplate. A tile placement station where the tiles are arranged on the coverplate. A tile aligning and securing station where the tiles are aligned relative to each other and the coverplate by the tile aligner and where the tiles are at least partially bonded to the coverplate. A tile assembly bonding material dispensing station where a bonding material is applied to a surface of the tiles opposite the side that the coverplate is bonded to. A backplate placement station where a backplate is arranged on the tiles.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: October 10, 2000
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Allan O. Johnson, Ramesh R. Kodnani, Mark V. Pierson, Edward J. Tasillo
  • Patent number: 6100114
    Abstract: Solder bumps on electronic components are encapsulated before attachment to a substrate or component carrier. A film of sealing material is pressed against top portions of the solder bumps by pressing with a layer of low durometer flexible material. Encapsulant is positioned between the component and the film and in contact with the bumps, and partially cured. The film and layer of flexible material are removed to expose the top portions of the encapsulated solder bumps.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: August 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: Cynthia S. Milkovich, Mark V. Pierson, Son K. Tran
  • Patent number: 6068175
    Abstract: Apparatus for connecting a first area array component to a substrate with a joining material. The apparatus has a nozzle directing heat toward both the first area array component and the portion of the substrate beneath the first area array component to melt the joining material. An elastic seal contacts the substrate and prevents the heat from affecting other components adjacent the first area array component. The nozzle is pressed against the substrate to restrain warping of the substrate, which might be caused by the heating of the first area array component, and to prevent damage to the substrate. The nozzle can tilt so that it conforms to the surface of the substrate. The first area array component is allowed to move freely in the direction of a plane of the substrate under the surface tension of the molten joining material during heating to center the first area array component.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: May 30, 2000
    Assignee: International Business Machines Corporation
    Inventors: Craig G. Heim, Russell H. Lewis, Mark V. Pierson, Karl J. Puttlitz
  • Patent number: 5980348
    Abstract: A method for aligning a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate is arranged on a coverplate support. A first layer of a bonding material is applied to at least one of a first side of each of the tiles and a surface of the coverplate on which the tiles are to be secured. The tiles are arranged on the coverplate, such that the first layer of bonding material is arranged between the tiles and the coverplate. The tiles are connected to an alignment apparatus. The tiles are aligned relative to each other and the coverplate. The tiles are at least partially secured to the coverplate.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: November 9, 1999
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Allan O. Johnson, Ramesh R. Kodnani, Mark V. Pierson, Edward J. Tasillo
  • Patent number: 5973389
    Abstract: A semiconductor chip carrier assembly which includes a flexible substrate having a metallicized path on one of its surfaces in electrical communication with a semiconductor chip. A stiffener is disposed adjacent to said flexible substrate and is bonded thereto by an adhesive composition. The adhesive composition which comprises a microporous film laden with a curable adhesive is disposed between the flexible substrate and the stiffener. A cover plate is adhesively bonded to the semiconductor chip and to the stiffener. A process of making the assembly involving disposition of the flexible substrate in a vacuum fixture upon which the adhesive composition and stiffener is placed followed by the application of heat and pressure to cure the curable adhesive is also described.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: October 26, 1999
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Culnane, Michael A. Gaynes, Ramesh R. Kodnani, Mark V. Pierson, Charles G. Woychik
  • Patent number: 5969945
    Abstract: A screen printing fixture holds a flexible circuit board having components attached to one side, to allow screening a pattern of solder paste onto the second side for subsequent attachment of components to that side. In an electronic package assembly a flexible circuit board with components is wound about a heat spreader assembly having a cavity so that at least one component on the flexible circuit board is positioned within the cavity and in thermal connection to the heat spreader.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: October 19, 1999
    Assignee: International Business Machines Corporation
    Inventors: Lawrence R. Cutting, Michael A. Gaynes, Eric A. Johnson, Cynthia S. Milkovich, Jeffrey S. Perkins, Mark V. Pierson, Steven E. Poetzinger, Jerzy Zalesinski
  • Patent number: 5889654
    Abstract: Integrated circuit chips (18, 42, or 56) are packaged within openings formed in a substrate such as PCMCIA Card (20, 40, or 54), thus allowing compliance with overall width dimension requirements for standardized electronic components. The arrangement has the advantages that thermal coefficient of expansion of the chips and cards match, and that a sturdy, multilayer ceramic substrate is used for electrical connection to electronic devices such as laptops, palmtops, and the like. In addition, a second integrated circuit chip (68) can be connected directly to the embedded chip (56), thereby allowing two chips to be accommodated in a card (54) at the same location and allowing chip-to-chip electrical communication. A variety of electrical bonding methods joining the embedded chip to the card can be employed. In addition, a variety of thermal conduction arrangements can be used for cooling the embedded integrated circuit chip.
    Type: Grant
    Filed: April 9, 1997
    Date of Patent: March 30, 1999
    Assignee: International Business Machines Corporation
    Inventors: Mark V. Pierson, Kenneth L. Spink, Jr., Thurston B. Youngs, Jr.
  • Patent number: 5889321
    Abstract: A stiffener (34 or 52 or 72) includes a pathway which allows gases and fluids, such as air, to be vented from the interface between surface bonding regions (35 or 60 or 74) of the stiffener and an adhesive (38 or 56 or 80) on a flexible substrate (36 or 54 or 78). The pathway may take the form of a porous material used for the stiffener or one or more bore holes (58 or 59 or 70) formed in the stiffener. The stiffener may also include an internal cavity (76) for promoting venting of fluids and gases. By venting fluid and gases from the adhesive/stiffener interface, better adhesion between the stiffener and flexible substrate is achieved.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: March 30, 1999
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Culnane, Michael A. Gaynes, Ramesh R. Kodnani, Mark V. Pierson
  • Patent number: 5875010
    Abstract: A display panel and method of making same in which the panel comprises a plurality of display devices mounted between light-transmitting plates. The structure includes clear and opaque bonding materials positioned to retain alignment and provide acceptable brightness, contrast, and resolution while holding the display devices in contact with the light-transmitting plates.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: February 23, 1999
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey C. Baechtle, Michael A. Gaynes, Mark V. Pierson, Anne M. Quinn, deceased, David B. Stone
  • Patent number: 5862588
    Abstract: A method for producing interconnect structures and circuit boards including placing an area array component having connection bumps on the corresponding metal contacts on a substrate disposed on a backing plate, providing heat curable joining material in communication with the bumps and contacts, contacting a gas nozzle directly to a portion of the substrate surrounding the component to press the substrate between the nozzle and the backing plate to restrain the substrate from wrapping, heating the component, the joining material and the substrate proximate the metal contacts while maintaining the nozzle on the substrate to cure the joining material, and cooling the component, the joining material and the substrate. Selected components can also be replaced utilizing the gas nozzle for restraining the substrate from wrapping.
    Type: Grant
    Filed: August 14, 1995
    Date of Patent: January 26, 1999
    Assignee: International Business Machines Corporation
    Inventors: Craig G. Heim, Russell H. Lewis, Mark V. Pierson, Karl J. Puttlitz
  • Patent number: 5831828
    Abstract: A multi-layer flexible circuit board has thicker regions to which surface-mount-technology (SMT) components (such as flip chips and QFPs) and pin-in-hole (PIH) components are mounted on both sides and which contains conductive through vias between wiring layers. After the SMT components have been mounted to the first side, a screening fixture with a support surface that has cavities conforming the components on the first side, is used to screen solder paste to the other side of the board. The thicker regions are surrounded by thinner regions of the board with fewer wiring layers and preferably fewer or thinner dielectric layers, and which can be bent along a line without bending the thicker regions. A common heat spreader plate with cavities or holes for multiple components is laminated to the thicker regions on one side of the board. The thicker regions have windows in which wire-bond chips are mounted to the heat spreader and the chips are wirebonded to the other side of the board.
    Type: Grant
    Filed: June 3, 1993
    Date of Patent: November 3, 1998
    Assignee: International Business Machines Corporation
    Inventors: Lawrence R. Cutting, Michael A. Gaynes, Eric A. Johnson, Cynthia S. Milkovich, Jeffrey S. Perkins, Mark V. Pierson, Steven E. Poetzinger, Jerzy Zalesinski
  • Patent number: 5759269
    Abstract: A screen printing machine comprising a backing plate with holes conforming to components attached to the surface of a flexible circuit board. The machine includes a screen which patterns solder paste on the surface of the circuit board while the circuit board is on the backing plate. Also included is a spring loaded element disposed adjacent to the backing plate which applies a predetermined continuous force to the four corners of the circuit board. This force is applied in a diagonal direction to the corners to stretch the circuit board so that the circuit board is parallel to the backing plate during screening.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: June 2, 1998
    Assignee: International Business Machines Corporation
    Inventors: Lawrence R. Cutting, Michael A. Gaynes, Eric A. Johnson, Cynthia S. Milkovich, Jeffrey S. Perkins, Mark V. Pierson, Steven E. Poetzinger, Jerzy Zalesinski
  • Patent number: 5638597
    Abstract: A multi-layer flexible circuit board has multiple thicker regions to which components are mounted and thinner, more flexible regions with fewer wiring layers through which the board can be bent about a line without bending thicker regions. Surface mount components such as QFP's and flip-chips are mounted on the front side, and surface mount and pin-in-hole components are mounted on the back side of the circuit board at the thick regions. Heat spreaders are laminated to the back sides of thicker regions. The thicker regions have windows in which wire bond chips are mounted on the heat spreader and wire bonded to the front side of the board. A thermally conductive adhesive or grease connects between the tops of the back side components and the bottoms of the cavities. The heat sinks are bolted together and/or to an enclosure frame to improve thermal performance.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 17, 1997
    Assignee: International Business Machines Corporation
    Inventors: Lawrence R. Cutting, Michael A. Gaynes, Eric A. Johnson, Cynthia S. Milkovich, Jeffrey S. Perkins, Mark V. Pierson, Steven E. Poetzinger, Jerzy Zalesinski
  • Patent number: 5565033
    Abstract: A method of applying bonding agents, such as solder pastes and conductive adhesives, to pad sites in the manufacture of electronic circuits uses a paste injection head. A permanent mask with cavity openings is applied around conductive pads on a carrier. The conductive pads correspond to chip attachment sites. The injection head is brought into contact with a surface of the mask, and pressure is applied to a bonding agent in the injection head. The injection head is then moved over the surface of the mask, filling cavity openings with the bonding agent. The injection head is then removed from the surface of the mask. If a solder paste is used, infrared radiation is applied to filled cavity openings to evaporate a paste flux and reflow solder to form solder balls within the cavity openings projecting above the mask. If a conductive adhesive is used, a stencil is applied to the surface of the mask prior to contacting the mask with said injection head.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: October 15, 1996
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, George D. Oxx, Mark V. Pierson, Jerzy Zalesinski
  • Patent number: 5545465
    Abstract: A method of applying bonding agents, such as solder pastes and conductive adhesives, to pad sites in the manufacture of electronic circuits uses a paste injection head. A permanent mask with cavity openings is applied around conductive pads on a carrier. The conductive pads correspond to chip attachment sites. The injection head is brought into contact with a surface of the mask, and pressure is applied to a bonding agent in the injection head. The injection head is then moved over the surface of the mask, filling cavity openings with the bonding agent. The injection head is then removed from the surface of the mask. If a solder paste is used, infrared radiation is applied to filled cavity openings to evaporate a paste flux and reflow solder to form solder balls within the cavity openings projecting above the mask. If a conductive adhesive is used, a stencil is applied to the surface of the mask prior to contacting the mask with said injection head.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: August 13, 1996
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, George D. Oxx, Mark V. Pierson, Jerzy Zalesinski
  • Patent number: 5528159
    Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: June 18, 1996
    Assignee: International Business Machine Corp.
    Inventors: Richard G. Charlton, George C. Correia, Mark A. Couture, Gary R. Hill, Kibby B. Horsford, Anthony P. Ingraham, Michael D. Lowell, Voya R. Markovich, Gordon C. Osborne, Jr., Mark V. Pierson
  • Patent number: 5523696
    Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.
    Type: Grant
    Filed: December 7, 1993
    Date of Patent: June 4, 1996
    Assignee: International Business Machines Corp.
    Inventors: Richard G. Charlton, George C. Correla, Mark A. Couture, Gary R. Hill, Kibby B. Horsford, Anthony P. Ingraham, Michael D. Lowell, Voya R. Markovich, Gordon C. Osborne, Jr., Mark V. Pierson
  • Patent number: 5478700
    Abstract: A method of applying bonding agents, such as solder pastes and conductive adhesives, to pad sites in the manufacture of electronic circuits uses a bonding agent injection head which includes a wiping guide, a blade which cooperates with the wiping guide to form an elongate nozzle slit, and an evacuation path ahead of the nozzle slit in a direction of movement of the injection head. A permanent mask with cavity openings is applied around conductive pads on a carrier. The conductive pads correspond to chip attachment sites. The injection head is brought into contact with a surface of the mask, and pressure is applied to a bonding agent in the injection head. The injection head is then moved over the surface of the mask, filling cavity openings with the bonding agent. The evacuation path ahead of the nozzle slit lets air out of the cavity openings as the cavity openings are filled with bonding agent. The injection head is then removed from the surface of the mask.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: December 26, 1995
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, George D. Oxx, Mark V. Pierson, Jerzy Zalesinski