Patents by Inventor Martin G. Dixon

Martin G. Dixon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9654281
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9654282
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9647831
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9641320
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9641319
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9634830
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9634828
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G Dixon, Srinivas Chennupaty, Michael E Kounavis
  • Method and apparatus to process SHA-2 secure hashing algorithm
    Patent number: 9632782
    Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Kirk S. Yap, Gilbert M. Wolrich, James D. Guilford, Vinodh Gopal, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • Flexible architecture and instruction for advanced encryption standard (AES)
    Patent number: 9634829
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • INSTRUCTION FOR PERFORMING AN OVERLOAD CHECK
    Publication number: 20170109160
    Abstract: A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether substantive data from a larger source data size will fit within a smaller data size that the substantive data is to flow to.
    Type: Application
    Filed: August 16, 2016
    Publication date: April 20, 2017
    Inventors: MARTIN G. DIXON, BAIJU V. PATEL, RAJEEV GOPALAKRISHNA
  • METHOD AND APPARATUS TO PROCESS SHA-2 SECURE HASHING ALGORITHM
    Publication number: 20170109162
    Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.
    Type: Application
    Filed: December 31, 2016
    Publication date: April 20, 2017
    Inventors: Kirk S. YAP, Gilbert M. WOLRICH, James D. GUILFORD, Vinodh GOPAL, Erdinc OZTURK, Sean M. GULLEY, Wajdi K. FEGHALI, Martin G. DIXON
  • APPARATUS AND METHOD FOR VECTOR INSTRUCTIONS FOR LARGE INTEGER ARITHMETIC
    Publication number: 20170060584
    Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 2, 2017
    Inventors: GILBERT M. WOLRICH, KIRK S. YAP, JAMES D. GUILFORD, ERDINC OZTURK, VINODH GOPAL, WAJDI K. FEGHALI, SEAN M. GULLEY, MARTIN G. DIXON
  • Apparatus and method of execution unit for calculating multiple rounds of a skein hashing algorithm
    Patent number: 9569210
    Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows: a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: February 14, 2017
    Assignee: Intel Corporation
    Inventors: Gilbert M. Wolrich, Kirk S. Yap, James D. Guilford, Erdinc Ozturk, Vinodh Gopal, Wajdi K. Feghali, Sean M. Gulley, Martin G. Dixon
  • Method and apparatus for a non-deterministic random bit generator (NRBG)
    Patent number: 9544139
    Abstract: A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: January 10, 2017
    Assignee: Intel Corporation
    Inventors: George W. Cox, David Johnston, Martin G. Dixon, Stephen A. Fischer, Jason W. Brandt
  • Instructions and Logic to Provide Memory Access Key Protection Functionality
    Publication number: 20160378692
    Abstract: Instructions and logic provide memory key protection functionality. Embodiments include a processor having a register to store a memory protection field. A decoder decodes an instruction having an addressing form field for a memory operand to specify one or more memory addresses, and a memory protection key. One or more execution units, responsive to the memory protection field having a first value and to the addressing form field of the decoded instruction having a second value, enforce memory protection according to said first value of the memory protection field, using the specified memory protection key, for accessing the one or more memory addresses, and fault if a portion of the memory protection key specified by the decoded instruction does not match a stored key value associated with the one or more memory addresses.
    Type: Application
    Filed: August 9, 2016
    Publication date: December 29, 2016
    Inventors: H. Peter Anvin, Martin G. Dixon
  • QoS based binary translation and application streaming
    Patent number: 9525586
    Abstract: In one embodiment, Quality of Service (QoS) criteria based server side binary translation and execution of applications is performed on multiple servers utilizing distributed translation and execution in either a virtualized or native execution environment. The translated applications are executed to generate output display data, the output display data is encoded in a media format suitable for video streaming, and the video stream is delivered over a network to a client device. In one embodiment, one or more graphics processors assist the central processors of the servers by accelerating the rendering of the application output, and a media encoder encodes the application output into a media format.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 20, 2016
    Assignee: Intel Corporation
    Inventors: Bharath Muthiah, William Bill Rash, Glenn Hinton, Martin G. Dixon, Scott Hayn, David Papworth
  • PROTECTED POWER MANAGEMENT MODE IN A PROCESSOR
    Publication number: 20160342196
    Abstract: In an embodiment, a processor includes a plurality of cores. Each core includes a core power unit to detect one or more power management events, and in response to the one or more power management events, initiate a protected power management mode in the core. Software interrupts to the core may be disabled during the protected power management mode. The core is to execute power management code during the protected power management mode. Other embodiments are described and claimed.
    Type: Application
    Filed: April 20, 2016
    Publication date: November 24, 2016
    Inventors: WILLIAM C. RASH, MARTIN G. DIXON, YAZMIN A. SANTIAGO
  • Method and apparatus for performing a shift and exclusive or operation in a single instruction
    Patent number: 9501281
    Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Erdinc Ozturk, Wajdi K. Feghali, Gilbert M. Wolrich, Martin G. Dixon
  • Method and apparatus for performing a shift and exclusive or operation in a single instruction
    Patent number: 9495165
    Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Erdinc Ozturk, Wajdi K. Feghali, Gilbert M. Wolrich, Martin G. Dixon
  • Method and apparatus for performing a shift and exclusive or operation in a single instruction
    Patent number: 9495166
    Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: November 15, 2016
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Erdinc Ozturk, Wajdi K. Feghali, Gilbert M. Wolrich, Martin G. Dixon