Patents by Inventor Martin G. Dixon

Martin G. Dixon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method, apparaturs, and system for speculative abort control mechanisms
    Publication number: 20160132334
    Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.
    Type: Application
    Filed: December 26, 2015
    Publication date: May 12, 2016
    Inventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, Ilhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
  • Method, apparatus, and system for speculative abort control mechanisms
    Publication number: 20160132336
    Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.
    Type: Application
    Filed: December 26, 2015
    Publication date: May 12, 2016
    Inventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, Ilhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
  • Method, apparatus, and system for speculative abort control mechanisms
    Publication number: 20160132337
    Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.
    Type: Application
    Filed: December 26, 2015
    Publication date: May 12, 2016
    Inventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, Ilhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
  • Method, Apparatus, And System For Speculative Abort Control Mechanisms
    Publication number: 20160132333
    Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.
    Type: Application
    Filed: December 26, 2015
    Publication date: May 12, 2016
    Inventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, Ilhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
  • Method, apparatus, and system for speculative abort control mechanisms
    Publication number: 20160132335
    Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.
    Type: Application
    Filed: December 26, 2015
    Publication date: May 12, 2016
    Inventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, IIhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119125
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119123
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119127
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119128
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119124
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119131
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119130
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119129
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • FLEXIBLE ARCHITECTURE AND INSTRUCTION FOR ADVANCED ENCRYPTION STANDARD (AES)
    Publication number: 20160119126
    Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
    Type: Application
    Filed: December 30, 2015
    Publication date: April 28, 2016
    Applicant: Intel Corporation
    Inventors: Gueron Shay, Wajdi K. Feghali, Vinodh Gopal, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
  • Supervisor mode execution protection
    Patent number: 9323533
    Abstract: Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Adriaan Van De Ven, Baiju V. Patel, Asit K. Mallick, Gilbert Neiger, James S. Coke, Martin G. Dixon, Jason W. Brandt
  • Processors, methods, and systems to relax synchronization of accesses to shared memory
    Patent number: 9304940
    Abstract: A processor of an aspect includes a plurality of logical processors. A first logical processor of the plurality is to execute software that includes a memory access synchronization instruction that is to synchronize accesses to a memory. The processor also includes memory access synchronization relaxation logic that is to prevent the memory access synchronization instruction from synchronizing accesses to the memory when the processor is in a relaxed memory access synchronization mode.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 5, 2016
    Assignee: Intel Corporation
    Inventors: Martin G. Dixon, William C. Rash, Yazmin A. Santiago
  • Instruction and logic to test transactional execution status
    Patent number: 9268596
    Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 23, 2016
    Assignee: Intel Corparation
    Inventors: Ravi Rajwar, Bret L. Toll, Konrad K. Lai, Matthew C. Merten, Martin G. Dixon
  • Instructions to perform JH cryptographic hashing in a 256 bit data path
    Patent number: 9270460
    Abstract: A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Gilbert M. Wolrich, Kirk S. Yap, Vinodh Gopal, James D. Guilford, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • Instructions to perform JH cryptographic hashing
    Patent number: 9251374
    Abstract: A method is described. The method includes executing one or more JH_SBOX_L instruction to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_Permute instruction to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 2, 2016
    Assignee: Intel Corporation
    Inventors: Kirk S. Yap, Gilbert M. Wolrich, Vinodh Gopal, James D. Guilford, Erdinc Ozturk, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon
  • SIMD integer multiply-accumulate instruction for multi-precision arithmetic
    Patent number: 9235414
    Abstract: A multiply-and-accumulate (MAC) instruction allows efficient execution of unsigned integer multiplications. The MAC instruction indicates a first vector register as a first operand, a second vector register as a second operand, and a third vector register as a destination. The first vector register stores a first factor, and the second vector register stores a partial sum. The MAC instruction is executed to multiply the first factor with an implicit second factor to generate a product, and to add the partial sum to the product to generate a result. The first factor, the implicit second factor and the partial sum have a same data width and the product has twice the data width. The most significant half of the result is stored in the third vector register, and the least significant half of the result is stored in the second vector register.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: January 12, 2016
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Gilbert M. Wolrich, Erdinc Ozturk, James D. Guilford, Kirk S. Yap, Sean M. Gulley, Wajdi K. Feghali, Martin G. Dixon