Patents by Inventor Martin LUEKER-BODEN
Martin LUEKER-BODEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11074318Abstract: An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.Type: GrantFiled: June 25, 2019Date of Patent: July 27, 2021Assignee: Western Digital Technologies, Inc.Inventors: Wen Ma, Pi-Feng Chiu, Minghai Qin, Won Ho Choi, Martin Lueker-Boden
-
Publication number: 20210192325Abstract: Techniques are presented for performing in-memory matrix multiplication operations for binary input, binary weight valued convolution neural network (CNN) inferencing. The weights of a filter are stored in pairs of memory cells of a storage class memory device, such as a ReRAM or phase change memory based devices. To reduce current consumption, the binary valued filters are transformed into ternary valued filters by taking sums and differences of binary valued filter pairs. The zero valued weights of the transformed filters are stored as a pair of high resistance state memory cells, reducing current consumption during convolution. The results of the in-memory multiplications are pair-wise combined to compensate for the filter transformations. To compensate for zero valued weights, a zero weight register stores the number of zero weights along each bit line and is used to initialize counter values for accumulating the multiplication operations.Type: ApplicationFiled: December 20, 2019Publication date: June 24, 2021Applicant: SanDisk Technologies LLCInventors: Tung Thanh Hoang, Won Ho Choi, Martin Lueker-Boden
-
Publication number: 20210181979Abstract: Apparatuses and techniques are described for reading crosspoint arrays of memory cells with high bandwidth and a relatively small page buffer. Multiple crosspoint arrays (XPAs) are read in parallel, with one memory cell per XPA being read, in a bank of XPAs. To reduce the read time, a row can be selected for the XPAs, after which memory cells in different columns are read, one column at a time, while the same row is selected. This avoids the need to transmit commands and a row address for re-selecting the row in each successive read operation. The XPAs may be ungrouped, or one XPA may be accessible at a time in a group. In one option, the XPAs are arranged in sets, either individually or in groups, and one set is accessible at a time.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Ward Parkinson, Raj Ramanujan, Martin Lueker-Boden
-
Publication number: 20210173560Abstract: Methods and apparatus are disclosed for implementing principal component analysis (PCA) within a non-volatile memory (NVM) die of solid state drive (SSD) to reduce the dimensionality of machine learning data before the data is transferred to other components of the SSD, such as to a data storage controller equipped with a machine learning engine. The machine learning data may include, for example, training images for training an image recognition system in which the SSD is installed. In some examples, the on-chip PCA components of the NVM die are configured as under-the-array or next-to-the-array components. In other examples, one or more arrays of the NVM die are configured as multiplication cores for performing PCA matrix multiplication. In still other aspects, multiple NVM dies are arranged in parallel, each with on-chip PCA components to permit parallel concurrent on-chip processing of machine learning data.Type: ApplicationFiled: December 6, 2019Publication date: June 10, 2021Inventors: Won Ho Choi, Yongjune Kim, Martin Lueker-Boden
-
Publication number: 20210110244Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement extends to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly. The arrangement further extends to a ternary-ternary network (TTN) by allowing 0 weight values in a unit synapse, maintaining the number of 0 weights in a register, and adjusting the count accordingly.Type: ApplicationFiled: October 15, 2019Publication date: April 15, 2021Applicant: SanDisk Technologies LLCInventors: Tung Thanh Hoang, Won Ho Choi, Martin Lueker-Boden
-
Publication number: 20210110235Abstract: Techniques are presented for accelerating in-memory matrix multiplication operations for a convolution neural network (CNN) inference in which the weights of a filter are stored in the memory of a storage class memory device, such as a ReRAM or phase change memory based device. To improve performance for inference operations when filters exhibit sparsity, a zero column index and a zero row index are introduced to account for columns and rows having all zero weight values. These indices can be saved in a register on the memory device and when performing a column/row oriented matrix multiplication, if the zero row/column index indicates that the column/row contains all zero weights, the access of the corresponding bit/word line is skipped as the result will be zero regardless of the input.Type: ApplicationFiled: October 15, 2019Publication date: April 15, 2021Applicant: SanDisk Technologies LLCInventors: Tung Thanh Hoang, Won Ho Choi, Martin Lueker-Boden
-
Publication number: 20200410334Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
-
Publication number: 20200411066Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.Type: ApplicationFiled: June 12, 2020Publication date: December 31, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
-
Publication number: 20200411065Abstract: An illustrative embodiment disclosed herein is an apparatus including a non-volatile memory cell and multi-bit input circuitry that simultaneously receives a plurality of bits, receives a supply voltage, converts the plurality of bits and the supply voltage into a multiply voltage, and applies the multiply voltage to the non-volatile memory cell. The non-volatile memory cell may pass a memory cell current in response to the multiply voltage. A magnitude of the multiply voltage may represent a multiplier. The memory cell current may represent a product of the multiplier and a multiplicand stored in the non-volatile memory cell.Type: ApplicationFiled: July 2, 2019Publication date: December 31, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
-
Publication number: 20200311512Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Wen Ma, Minghai Qin, Gerrit Jan Hemink, Martin Lueker-Boden
-
Publication number: 20200311523Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter. The arrangement can be extended to ternary inputs to realize a ternary-binary network (TBN) by adding a circuit to detect 0 input values and adjust the accumulated count accordingly.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Applicant: SanDisk Technologies LLCInventors: Tung Thanh Hoang, Won Ho Choi, Martin Lueker-Boden
-
Publication number: 20200257936Abstract: Exemplary methods and apparatus are disclosed that implement super-sparse image/video compression by storing image dictionary elements within a cross-bar resistive random access memory (ReRAM) array (or other suitable cross-bar NVM array). In illustrative examples, each column of the cross-bar ReRAM array stores the values for one dictionary element (such as one 4×4 dictionary element). Methods and apparatus are described for training (configuring) the cross-bar ReRAM array to generate and store the dictionary elements by sequentially applying patches from training images to the array using an unstructured Hebbian training procedure. Additionally, methods and apparatus are described for compressing an input image by applying patches from the input image to the ReRAM array to read out cross-bar column indices identifying the columns storing the various dictionary elements that best fit the image. This may be done in parallel using a set of ReRAM arrays.Type: ApplicationFiled: February 13, 2019Publication date: August 13, 2020Inventors: Wen Ma, Minghai Qin, Won Ho Choi, Pi-Feng Chiu, Martin Lueker-Boden
-
Publication number: 20200192970Abstract: An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.Type: ApplicationFiled: June 25, 2019Publication date: June 18, 2020Inventors: Wen Ma, Pi-Feng Chiu, Minghai Qin, Won Ho Choi, Martin Lueker-Boden
-
Patent number: 10643119Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.Type: GrantFiled: May 7, 2019Date of Patent: May 5, 2020Assignee: SanDisk Technologies LLCInventors: Pi-Feng Chiu, Won Ho Choi, Wen Ma, Martin Lueker-Boden
-
Patent number: 10643705Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit. The approach can be extended from binary weights to multi-bit weight values by use of multiple differential memory cells for a weight.Type: GrantFiled: May 16, 2019Date of Patent: May 5, 2020Assignee: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Wen Ma, Martin Lueker-Boden
-
Publication number: 20200117982Abstract: Enhanced techniques and circuitry are presented herein for artificial neural networks. These artificial neural networks are formed from artificial synapses, which in the implementations herein comprise a memory arrays having non-volatile memory elements. In one implementation, an apparatus comprises a plurality of non-volatile memory arrays configured to store weight values for an artificial neural network. Each of the plurality of non-volatile memory arrays can be configured to receive data from a unified buffer shared among the plurality of non-volatile memory arrays, operate on the data, and shift at least portions of the data to another of the plurality of non-volatile memory arrays.Type: ApplicationFiled: March 15, 2019Publication date: April 16, 2020Inventors: Pi-Feng Chiu, Won Ho Choi, Wen Ma, Martin Lueker-Boden
-
Publication number: 20200034686Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.Type: ApplicationFiled: May 7, 2019Publication date: January 30, 2020Applicant: SanDisk Technologies LLCInventors: Pi-Feng Chiu, Won Ho Choi, Wen Ma, Martin Lueker-Boden
-
Publication number: 20200034697Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.Type: ApplicationFiled: March 28, 2019Publication date: January 30, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Wen Ma, Minghai Qin, Gerrit Jan Hemink, Martin Lueker-Boden
-
Publication number: 20200035305Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit. The approach can be extended from binary weights to multi-bit weight values by use of multiple differential memory cells for a weight.Type: ApplicationFiled: May 16, 2019Publication date: January 30, 2020Applicant: SanDisk Technologies LLCInventors: Won Ho Choi, Pi-Feng Chiu, Wen Ma, Martin Lueker-Boden
-
Patent number: 10528643Abstract: Technology is described herein for performing multiplication using non-volatile memory cells. A multiplicand may be stored a node that includes multiple non-volatile memory cells. Each memory cell in a node may be programmed to one of two physical states, with each non-volatile memory cell storing a different bit of the multiplicand. Multiplication may be performed by applying a multiply voltage to the node of memory cells and processing memory cell currents from the memory cells in the node. The memory cell current from each memory cell in the node is multiplied by a different power of two. The multiplied signals are summed to generate a “result signal,’ which represents a product of the multiplier and a multiplicand stored in the node. If desired, “binary memory cells” may be used to perform multiplication. Vector/vector and vector/matrix multiplication may also be performed.Type: GrantFiled: August 1, 2018Date of Patent: January 7, 2020Assignee: SanDisk Technologies LLCInventors: Won Ho Choi, Martin Lueker-Boden