Abstract: Apparatuses, systems, methods, and computer program products are disclosed for memory array addressing. An addressing circuit is configured to receive an address for an operation on an array of multiple memory regions. An address includes a row address and a column address both multiplexed into the address and received with an activate command for an operation. A row buffer for an array of multiple memory regions is configured to store data identified by multiplexed row and column addresses from the multiple memory regions. Data of an operation is selected from a row buffer based on a second address received with a subsequent command for the operation.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for memory array addressing. An addressing circuit is configured to receive an address for an operation on an array of multiple memory regions. An address includes a row address and a column address both multiplexed into the address and received with an activate command for an operation. A row buffer for an array of multiple memory regions is configured to store data identified by multiplexed row and column addresses from the multiple memory regions. Data of an operation is selected from a row buffer based on a second address received with a subsequent command for the operation.

Abstract: A method and system for performing operations in a canary-based communication protocol; specifically, an acknowledgment-less scheme to reduce completion latency and increase effective bandwidth utilization on a computer expansion bus is disclosed. In one embodiment, a host selects a canary to represent whether a data stream of unknown content has been received. The host sends the canary to the target over a communication protocol and then marks a portion of a memory buffer with the same canary. Since the data may be unknown, the canary chosen could be the same value as the data. As such, when processing a request and transmitting data back to the host, the target can do real-time detection to determine whether a canary collision will occur. If a collision does occur, the target can remedy the collision without the need to time out and retry the operation.

Abstract: A method and system for accessing a driverless storage device via a byte-addressable protocol. Properly leveraging real-time queue polling between a CPU and Non-Volatile Memory (“NVM”) requires significant, complex, customized software and elaborate device drivers that consume operating systems. The present system maximizes existing host operating systems and memory management hardware and makes the NVM appear as simple memory to a CPU, reducing submission and completion latency and increasing effective bandwidth utilization. In one embodiment, a fast serial protocol translates storage in a target into a byte-addressable memory aperture. The fast serial protocol exposes byte-addressable memory aperture to a memory address range in a host. The host, in communication with a controller, sends a single request for data and receives, from the controller in communication with the storage medium, the data.