Patents by Inventor MaryJane Brodsky
MaryJane Brodsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9059315Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.Type: GrantFiled: January 2, 2013Date of Patent: June 16, 2015Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, Inc.Inventors: Takashi Ando, Maryjane Brodsky, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Joseph F. Shepard, Jr., Yanfeng Wang, Jinping Liu
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Patent number: 9040399Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.Type: GrantFiled: October 27, 2011Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
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Patent number: 9029959Abstract: A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.Type: GrantFiled: June 29, 2012Date of Patent: May 12, 2015Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Michael P. Chudzik, Min Dai, Joseph F. Shepard, Jr., Shahab Siddiqui, Yanfeng Wang, Jinping Liu
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Patent number: 8952460Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.Type: GrantFiled: November 12, 2013Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Murshed M. Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha, Shahab Siddiqui
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Patent number: 8809152Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.Type: GrantFiled: November 18, 2011Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Murshed M. Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha, Shahab Siddiqui
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Publication number: 20140187028Abstract: Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.Type: ApplicationFiled: January 2, 2013Publication date: July 3, 2014Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Maryjane Brodsky, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Joseph F. Shepard, JR., Yanfeng Wang, Jinping Liu
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Publication number: 20140061819Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.Type: ApplicationFiled: November 12, 2013Publication date: March 6, 2014Applicant: International Business Machines CorporationInventors: MaryJane Brodsky, Murshed M. Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha, Shahab Siddiqui
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Publication number: 20140001570Abstract: A composite high dielectric constant (high-k) gate dielectric includes a stack of a doped high-k gate dielectric and an undoped high-k gate dielectric. The doped high-k gate dielectric can be formed by providing a stack of a first high-k dielectric material layer and a dopant metal layer and annealing the stack to induce the diffusion of the dopant metal into the first high-k dielectric material layer. The undoped high-k gate dielectric is formed by subsequently depositing a second high-k dielectric material layer. The composite high-k gate dielectric can provide an increased gate-leakage oxide thickness without increasing inversion oxide thickness.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MaryJane Brodsky, Michael P. Chudzik, Min Dai, Joseph F. Shepard, JR., Shahab Siddiqui, Yanfeng Wang, Jinping Liu
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Publication number: 20130126986Abstract: A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MaryJane Brodsky, Murshed M. Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan, Shreesh Narasimha, Shahab Siddiqui
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Publication number: 20130105894Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.Type: ApplicationFiled: October 27, 2011Publication date: May 2, 2013Applicant: International Business Machines CorporationInventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
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Publication number: 20130105896Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor.Type: ApplicationFiled: September 24, 2012Publication date: May 2, 2013Applicant: International Business Machines CorporationInventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
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Patent number: 8198169Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.Type: GrantFiled: December 21, 2010Date of Patent: June 12, 2012Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Kevin R. Winstel
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Publication number: 20110092043Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.Type: ApplicationFiled: December 21, 2010Publication date: April 21, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MaryJane Brodsky, Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Kevin R. Winstel
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Patent number: 7888723Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.Type: GrantFiled: January 18, 2008Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Kevin R. Winstel
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Patent number: 7875919Abstract: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.Type: GrantFiled: March 31, 2008Date of Patent: January 25, 2011Assignee: International Business Machines CorporationInventors: Roger A. Booth, Jr., MaryJane Brodsky, Kangguo Cheng, Chengwen Pei
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Patent number: 7759766Abstract: A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.Type: GrantFiled: August 22, 2007Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Roger A. Booth, Jr., MaryJane Brodsky, Kangguo Cheng, Chengwen Pei
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Patent number: 7671394Abstract: A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.Type: GrantFiled: October 17, 2007Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Roger A. Booth, Jr., MaryJane Brodsky, Kangguo Cheng, Chengwen Pei
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Publication number: 20090242953Abstract: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roger A. Booth, JR., MaryJane Brodsky, Kangguo Cheng, Chengwen Pei
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Publication number: 20090184356Abstract: A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.Type: ApplicationFiled: January 18, 2008Publication date: July 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MaryJane Brodsky, Kangguo Cheng, Herbert L. Ho, Paul C. Parries, Kevin R. Winstel
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Publication number: 20090101956Abstract: A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.Type: ApplicationFiled: October 17, 2007Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roger A. Booth, JR., MaryJane Brodsky, Kangguo Cheng, Chengwen Pei