Patents by Inventor Masaaki Kamiya
Masaaki Kamiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6040200Abstract: A method of fabricating a light valve device comprises forming a substrate having stacked layers including a light-shielding thin film layer, an insulating film, and a single crystalline semiconductor thin film stacked in this order on a transparent support substrate. A light-shielding layer pattern is formed by selectively etching the stacked layers. Thereafter, a switching element is formed comprised of a transistor having a channel region formed in the single crystalline semiconductor thin film and a main gate electrode covering the channel region. The channel region is provided over the light-shielding pattern layer to prevent light incident from the transparent support substrate from illuminating the channel region to suppress a photo-induced leakage current in the channel region. A transparent electrode is formed and is electrically connected to the switching element.Type: GrantFiled: April 14, 1997Date of Patent: March 21, 2000Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
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Patent number: 6028338Abstract: A semiconductor integrated circuit device has a peripheral transistor having a strengthened ESD resistance for external connection. The peripheral transistor has a channel structure effective to release an electrostatic stress current more efficiently than an internal transistor of the semiconductor integrated circuit. In one embodiment, the peripheral transistor has a channel portion that is shorter than the channel portion of an internal transistor. In another embodiment, the peripheral transistor has a substrate contact, a ground line, and an additional resistor interconnection between them to efficiently release an electrostatic stress current. In another embodiment, the peripheral transistor has an asymmetric channel structure so that the distance between the source contact and the gate electrode is set shorter than the distance between the drain contact and the gate electrode.Type: GrantFiled: June 5, 1995Date of Patent: February 22, 2000Assignee: Seiko Instruments Inc.Inventors: Yutaka Saito, Jun Osanai, Yoshikazu Kojima, Masaaki Kamiya
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Patent number: 5982461Abstract: A light valve device has a drive substrate integrated with a drive electrode. A transistor is connected to the drive electrode and a driving circuit energizes the drive electrode through the transistor. An opposed substrate is provided opposed to the drive electrode, and an electrooptical material layer is disposed between the drive substrate and the opposed substrate. The drive substrate has a structure comprising a substrate layer and a semiconductor single crystal thin film layer. The semiconductor single crystal thin film layer is made by thinning a semiconductor single crystal wafer which has been bonded to the substrate layer. The light valve device has a small size and high pixel density and can be formed using miniaturization technology. The light valve can be used for a small size, high resolution video projector and a color matrix display device.Type: GrantFiled: February 14, 1992Date of Patent: November 9, 1999Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
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Patent number: 5926699Abstract: A method of fabricating a semiconductor device comprises the steps of sequentially forming a first gate electrode and an insulating film over a transparent support substrate, forming a through-hole in the insulating film, forming a semiconductor single crystal silicon thin film over the transparent support substrate by epitaxial growth in the through-hole of the insulating film, forming a transistor element having a channel region formed in the semiconductor single crystal silicon thin film, and forming a second gate electrode over and electrically insulated from the channel region of the transistor element.Type: GrantFiled: June 2, 1998Date of Patent: July 20, 1999Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
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Patent number: 5851909Abstract: An impurity adsorption layer is formed on a substrate surface and solid-phase thermal diffusion is carried out to form source and drain regions for a metal-insulator-semiconductor field-effect-transistor having lightly doped drain structure or double doped drain structure. The thus formed impurity-doped region is ultrashallow, thereby producing high speed semiconductor devices of small dimensions.Type: GrantFiled: January 19, 1993Date of Patent: December 22, 1998Assignee: Seiko Instruments Inc.Inventors: Masaaki Kamiya, Kenji Aoki, Naoto Saito
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Patent number: 5825064Abstract: The semiconductor nonvolatile memory has integrated memory cells, each being operative to carry out writing and reading of information in random-access basis and having an electric charge storage structure effective to memorize the information in nonvolatile state. The information is temporarily written into each memory cell in volatile state, and thereafter the temporarily written information is written at one into the respective electric charge storage structure of each memory cell, thereby effecting quick writing of nonvolatile information into the respective memory cells of multi-bits.Type: GrantFiled: March 3, 1993Date of Patent: October 20, 1998Assignee: Agency of Industrial Science and Technology and Seiko Instruments Inc.Inventors: Yutaka Hayashi, Yoshikazu Kojima, Ryoji Takada, Masaaki Kamiya
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Patent number: 5759878Abstract: A method of fabricating a semiconductor device comprises the steps of preparing a transparent support substrate, forming a first gate electrode comprising semiconductor single crystal silicon by epitaxial growth on the transparent support substrate, forming an insulating film over the first gate electrode, forming a through-hole in the insulating film to expose a portion of the first gate electrode, laterally and epitaxially growing a semiconductor single crystal silicon thin film over the transparent substrate by epitaxial growth in the through-hole of the insulating film, forming a transistor element having a channel region formed in the semiconductor single crystal silicon thin film, and forming a second gate electrode over and electrically insulated from the channel region.Type: GrantFiled: June 29, 1995Date of Patent: June 2, 1998Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
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Patent number: 5672518Abstract: The invention provides a semi-conductor light valve device and a process for fabricating the same. The device comprises a composite substrate having a supporte substrate, a light-shielding thin film formed on said supporte substrate and semiconductive thin film disposed on the light-shielding thin film with interposing an insulating thin film. A switching element made of a transistor and a transparent electrode for driving light valve are formed on the semiconductive thin film, and the switching element and the transparent electrode are connected electrically with each other. The transistor includes a channel region in the semiconductive thin film and a main gate electrode for controlling the conduction in the channel region, and the light-shielding thin film layer is so formed as to cover the channel region on the side opposite to said channel region, so as to prevent effectively a back channel and shut off the incident light.Type: GrantFiled: May 7, 1993Date of Patent: September 30, 1997Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
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Patent number: 5672906Abstract: The present invention is provided for improving latch-up resistance in a semiconductor integrated circuit device employing CMOS structure, for preventing the photoelectric carriers from getting into the sensors and improving the afterimage characteristic in a semiconductor image sensor device, and for impurity the switching characteristic in a semiconductor device having bipolar element. An electron beam of over 2 MeV and 1E15/cm.sup.2 is irradiated to a monocrystal silicon semiconductor region in a substrate and then annealing is performed at a high temperature of over 200.degree. C. As a result, at 150 K., a shallow level traps of which the activation energy from a valence band EV is under 0.1 eV and which is produced at the concentration of about 1.2-1.7E15/cm.sup.3, and a deep level traps of which the activation energy is 0.28-0.32 eV and which is produced at the concentration of about 1.6-2.0E13/cm.sup.3 are obtained.Type: GrantFiled: January 18, 1996Date of Patent: September 30, 1997Assignee: Seiko Instruments Inc.Inventors: Yutaka Saito, Takao Akiba, Koju Nonaka, Masaaki Kamiya, Hitomi Watanabe
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Patent number: 5637187Abstract: A process for forming a light valve device comprises forming a semiconductor single crystal film to form a composite substrate by polishing a semiconductor single crystal substrate after an electric insulating substrate has been bonded thereto; forming a group of pixel electrodes for defining a pixel region and a group of switch elements for selectively energizing the pixel electrodes by integrating a pixel array portion over the composite substrate; forming a liquid crystal aligning means for the pixel region; superposing an opposed substrate over the composite substrate with a gap therebetween; and filling the gap with liquid crystal material.Type: GrantFiled: June 5, 1995Date of Patent: June 10, 1997Assignee: Seiko Instruments Inc.Inventors: Hiroaki Takasu, Yoshikazu Kojima, Masaaki Kamiya, Tsuneo Yamazaki, Hiroshi Suzuki, Masaaki Taguchi, Ryuichi Takano, Satoru Yabe
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Patent number: 5585304Abstract: A semiconductor wafer is comprised of a transparent layer interposed between a thin silicon layer and a thick silicon layer. Silicon islands are formed from the thin silicon layer on the transparent layer. Device elements are formed in the silicon islands. Thereafter, the thick silicon layer which is a support layer is etched away to form a transparent region on the wafer. The wafer is constructed to avoid elimination or destruction of the transparent layer during the course of formation of the silicon islands and during the course of etching of the rear thick silicon plate. The transparent layer is comprised of a silicon nitride film or a silicon carbide film. Alternatively, the transparent layer is comprised of a silicon oxide film covered by a silicon nitride film or a silicon carbide film on one or both of the upper and lower faces of the silicon oxide film.Type: GrantFiled: August 2, 1994Date of Patent: December 17, 1996Assignees: Agency Industrial Science, Seiko Instruments Inc.Inventors: Yutaka Hayashi, Kunihiro Takahashi, Hiroaki Takasu, Yoshikazu Kojima, Hitoshi Niwa, Nobuyoshi Matsuyama, Yomoyuki Yoshino, Masaaki Kamiya
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Patent number: 5486716Abstract: A semiconductor integrated circuit device has a peripheral transistor having a strengthened ESD resistance for external connection. The peripheral transistor has a channel structure effective to release an electrostatic stress current more efficiently than an internal transistor of the semiconductor integrated circuit. In one embodiment, the peripheral transistor has a channel portion that is shorter than the channel portion of an internal transistor. In another embodiment, the peripheral transistor has a substrate contact, a ground line, and an additional resistor interconnection between them to efficiently release an electrostatic stress current. In another embodiment, the peripheral transistor has an asymmetric channel structure so that the distance between the source contact and the gate electrode is set shorter than the distance between the drain contact and the gate electrode.Type: GrantFiled: May 8, 1992Date of Patent: January 23, 1996Assignee: Seiko Instruments Inc.Inventors: Yutaka Saito, Jun Osanai, Yoshikazu Kojima, Masaaki Kamiya
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Patent number: 5463238Abstract: A semiconductor device comprises a complementary MOS transistor integrated circuit formed in a semiconductor single crystal silicon disposed on an electrically insulating layer. A thickness of the single crystal silicon in a region in which an N-type MOS transistor is formed is made thicker than the thickness in a region in which a P-type MOS transistor is formed. By this structure, the bottoms of the source region and the drain region of the N-type transistor are separated from the electrically insulating layer by a predetermined distance. The separation of the source region and the drain region from the electrically insulating layer is effective to prevent a parasitic channel from forming, thereby reducing leakage current and making the semiconductor device more efficient.Type: GrantFiled: February 25, 1993Date of Patent: October 31, 1995Assignee: Seiko Instruments Inc.Inventors: Kunihiro Takahashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
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Patent number: 5233211Abstract: The invention provides a semi-conductor light valve device and a process for fabricating the same. The device comprises a composite substrate having a supporte substrate, a light-shielding thin film formed on said supporte substrate and semiconductive thin film disposed on the light-shielding thin film with interposing an insulating thin film. A switching element made of a transistor and a transparent electrode for driving light valve are formed on the semiconductive thin film, and the switching element and the transparent electrode are connected electrically with each other. The transistor includes a channel region in the semiconductive thin film and a main gate electrode for controlling the conduction in the channel region, and the light-shielding thin film layer is so formed as to cover the channel region on the side opposite to said channel region, so as to prevent effectively a back channel and shut off the incident light.Type: GrantFiled: October 4, 1991Date of Patent: August 3, 1993Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
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Patent number: 5136540Abstract: A nonvolatile memory has integrated memory cells each operative to carry out writing and reading of information on a random-access basis and each having an electric charge storage structure effective to memorize the information in a nonvolatile state. The information is temporarily written into each memory cell in a volatile state, and thereafter the temporarily written information is written at once into a respective electric charge storage structure of each memory cell, thereby effecting high speed writing of nonvolatile information into the respective memory cells.Type: GrantFiled: March 12, 1990Date of Patent: August 4, 1992Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.Inventors: Yutaka Hayashi, Yoshikazu Kojima, Ryoji Takada, Masaaki Kamiya
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Patent number: 5122847Abstract: A non-volatile semiconductor memory device is comprised of a floating gate electrode disposed on and electrically insulated from a semiconductor substrate for storing electric charge. A tunnel insulating film is disposed in contact with the floating gate electrode to inject and extract the electric charge to and from the floating gate electrode in the form of an electric tunnel current flowing through the tunnel insulating film. The tunnel insulating film is composed of silicon oxide chemically-vapor-deposited at a temperature between 700.degree. C. and 900.degree. C. from the vapor mixture of dichlorosilane and dinitrogen monoxide on the order of 100 .ANG. thickness to thereby establish a breakdown current density more than 1.0 A/cm.sup.2.Type: GrantFiled: September 7, 1988Date of Patent: June 16, 1992Assignee: Seiko Instruments & Electronics Ltd.Inventors: Masaaki Kamiya, Yukihiro Imura, Katsuyuki Takahashi
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Patent number: 5100698Abstract: The invention relates to the application of a releasing agent to a surface of a glass plate which is to be subsequently bent in a heated state together with another glass plate thereon. The glass plate is held in a standing posture, and hot air is blown perpendicularly against a surface of the glass plate, and simultaneously an aqueous solution of a releasing agent is sprayed from a plurality of spray nozzles into a space in front of the glass plate surface such that the sprayed solution mixes with the hot air before arriving at the glass plate surface. In an embodiment the spray nozzles are directed parallel to the glass plate or obliquely so as to make a small acute angle with the glass plate and arranged such that the hot air forces droplets of the sprayed solution to move toward the glass plate surface together with the hot air. In another embodiment the spray nozzles are directed perpendicularly toward the glass plate and arranged such that the sprayed solution soon mixes with the hot air.Type: GrantFiled: December 19, 1990Date of Patent: March 31, 1992Assignee: Central Glass Company, LimitedInventors: Masaaki Kamiya, Masami Nishitani
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Patent number: 4943943Abstract: The present invention provides a read-out circuit for a nonvolatile memory which is capable of extracting a widely-fluctuating output voltage, even when the threshold value of the nonvolatile memory changes only a little.Type: GrantFiled: July 24, 1984Date of Patent: July 24, 1990Inventors: Yutaka Hayashi, Yoshikazu Kojima, Masaaki Kamiya, Kojiro Tanaka
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Patent number: 4875011Abstract: Two Hall effect devices are formed on a major surface of a silicon single crystal substrate lying in parallel to the (100) crystalline plane and series-connected to form a magnetic sensor. Each of the Hall effect devices has a pair of drive electrodes spaced apart from each other in a direction substantially parallel to the <100> or <010> crystalline axis and held at different potentials for flowing therebetween a drive current in said direction to drive the Hall effect device and a pair of Hall terminals for developing a Hall voltage when exposed to an external magnetic field. A comparator compares the potentials of two selected Hall terminals of the different Hall devices with each other to produce a compared signal. A switching element is connected to one of the Hall devices to control the potential of the Hall terminals to equalize the potentials of the two selected Hall terminals in response to the compared signal.Type: GrantFiled: March 4, 1987Date of Patent: October 17, 1989Assignee: Seiko Instruments Inc.Inventors: Masayuki Namiki, Masanori Gouda, Masaaki Kamiya
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Patent number: 4821236Abstract: A floating gate type semiconductor non-volatile memory injects carriers from a carrier supply region to a floating gate by a phenomenon called "punch-through" injection in which a space charge region is formed in a semiconductor substrate between the carrier supply region and a carrier injection region so as to accelerate the carriers and inject them into the floating gate without forwardly biasing the carrier injection region or the substrate.Type: GrantFiled: February 9, 1987Date of Patent: April 11, 1989Assignees: Kogyo Gizyutsuin, Seiko Instruments & Electronics Ltd.Inventors: Yutaka Hayashi, Yoshikazu Kojima, Masaaki Kamiya, Kojiro Tanaka