Abstract: A non-volatile semiconductor memory device has source and drain regions disposed in spaced apart relation adjacent the surface of a semiconductor substrate to define in the substrate a channel region having a first channel region portion in contract with the drain region and a second channel region portion between the first channel region portion and the source region. A floating gate electrode is disposed over the channel region between the source and drain regions, and a gate insulating layer is disposed between the channel region and the floating gate electrode.

Abstract: Two Hall effect devices are series-connected to form a magnetic sensor. Each of the Hall effect devices has a pair of Hall terminals for developing a Hall voltage when exposed to an external magnetic field. A comparator compares the potentials of two selected Hall terminals of the different Hall devices with each other to produce a compared signal. A switching element is connected to one of the Hall devices to control the potential of the Hall terminals to equalize the potentials of the two selected Hall terminals in response to the compared signal. Two non-selected Hall terminals develop positive and negative Hall voltages, respectively, relative to the selected Hall terminals so that the magnetic sensor produces a totalized Hall voltage of the two Hall effect devices.

Abstract: A thermosensitive semiconductor device has a semiconductor substrate of one conductivity type which is used as the common collector of at least two Darlington-connected transistors. The base of the first stage transistor is connected to the common collector to form a first terminal and the emitter of the final stage transistor forms a second terminal. A constant current source is connected between the first and second terminals. To reduce deviations in the temperature response, a second collector region can be used and which can extend to a depth deeper than the depth of the emitter of the final stage transistor to absorb some of the carriers injected by the emitter.

Abstract: This invention relates to the reduction of programming voltage in a non-volatile memory of the type having a double gate structure composed of a select-gate and a floating-gate. A channel region under the select-gate is highly doped and a channel region under the floating gate is lightly doped or doped to opposite conductivity type. Due to the different doping concentrations between these two channel regions, a large and steep surface potential gap appears at the transition region between the select-gate and the floating-gate in the programming operation thereby reducing the programming voltage.

Abstract: In the non-volatile semiconductor memory of present invention, a select gate and a floating gate are formed on the surface portion of the substrate between a source region and the drain region also acting as a control gate through a gate oxide film. A part of a channel current is injected into the floating gate at the surface portion under the edge of the floating gate covered by the select gate.

Abstract: A temperature detecting device comprises a semiconductor diode temperature sensor having a resistance characteristic which varies with variations in temperature, and a constant current circuit connected in series. A power source is connected in parallel with the series circuit and connected in parallel with a constant voltage circuit. A resistance ladder circuit is connected between an output terminal of the constant voltage circuit and one terminal of the power source, and an output terminal of the resistance ladder circuit is connected to a first input terminal of a differential amplifier. A second input terminal of the differential amplifier is connected to a connection point of the semiconductor diode and the constant current circuit.

Abstract: A constant current circuit comprising first and second insulated gate field effect transistors connected in series, and third and fourth insulated gate field effect transistors connected in series. The series connected transistor pairs are connected in parallel. The first and third transistors have different threshold voltages, and have their respective gate electrodes connected together, and the second and fourth transistors have equal threshold voltages and have their respective gate electrodes connected together. The gate of the second transistor is connected to the node between the first and second transistors, and the gate of the third transistor is connected to the node between the third and fourth transistors.

Abstract: A battery voltage detecting circuit for detecting a low battery voltage condition. A memory stores a reference digital voltage signal defining a digital value of a reference voltage level of a battery. A battery voltage measuring circuit digitally measures battery voltage and develops a digital voltage output signal representative of the measured battery voltage. The battery voltage measuring circuit includes a voltage-pulse signal generator which generates a number of pulses representative of battery voltage, and a counter circuit for counting the pulses and for developing a digital count representative of the measured battery voltage. A digital comparator circuit compares the refrence digital voltage signal and the digital voltage signal representing battery voltage for comparing the same and for developing an output signal when the digital voltage signal representing battery voltage coincides with the reference digital voltage signal.

Abstract: The output voltage of a power source is converted into a time signal by a circuit comprising a capacitor to which the voltage is applied, an MOS-FET connected across the capacitor and controlling its discharge rate in accordance with the voltage of the power source and a switching circuit which controls the MOS-FET. The time period representing the voltage of the power source is displayed digitally by counting the number of standard pulses occurring during the time period and digitally displaying the pulse count.

Abstract: A booster circuit for a liquid crystal display device of a timepiece is disclosed. The booster circuit is a sort of a blocking oscillator having a transformer of which turns ratio is 1 : n (where n is a real number). The rectified output voltage of said blocking oscillator is superposed on the voltage of the cell so that the output voltage of the booster circuit is higher than of the blocking oscillator. A smoothing condenser has ample capacitance to have a larger time constant than the fluctuation time of the voltage of the cell owing to mechanical shock.