Abstract: Provided is a method for producing a positive electrode active material for an alkali ion secondary battery, the positive electrode active material containing a large amount of a transition metal and enabling operation of the battery. In the method for producing a positive electrode active material for an alkali ion secondary battery, in which the positive electrode active material contains 34 mol % or more of CrO+FeO+MnO+CoO+NiO, the method includes: a step of preparing a positive electrode active material precursor containing crystals; and a step of irradiating the positive electrode active material precursor with light to melt the crystals and amorphize at least a portion of the positive electrode active material precursor.

Abstract: A seating state detection device includes an acquisition unit configured to acquire a detection signal group in a predetermined period that is output as a result of transmission and reception of waves by a radio wave sensor mounted on a vehicle, a signal extraction unit configured to extract specific-intensity signals in a predetermined reflection intensity range from the detection signal group, and a determination unit configured to determine whether an occupant in the vehicle is in a first riding state in which the occupant is directly seated on a seat or in a second riding state in which the occupant is seated in an infant auxiliary device, based on a distribution mode of the specific-intensity signals.

Abstract: A parallel processing apparatus comprises a plurality of arithmetic processors and a plurality of storages. A first processor executes first processing included in parallel processing by using first unit of processing, a second processor executes second processing by using second unit of processing, a first storage stores first information and a second storage stores second information, each to be used by the first and the second processors in an aggregate operation, the first information contains first parent information indicating that the second unit of processing is a parent of the first unit of processing, the second information contains first child information indicating that the first unit of processing is a child of the second unit of processing, and the first processor transmits an end notification to the second processor when the first processing is ended and the first information does not contain information indicating a child of the first unit.

Abstract: A procedure includes extracting a divisible layer among a plurality of layers included in a machine learning model, based on a definition of the machine learning model and information regarding a machine learning execution environment that includes information regarding a plurality of calculation nodes that performs machine learning by using the machine learning model, and determining a division type and a number of divisions that are available in each extracted divisible layer, obtaining an operation amount for each of the calculation nodes, based on the division type and the number of divisions, obtaining a communication cost and an operation cost of the machine learning model after division of the divisible layer, based on the division type and the number of divisions, and presenting the operation amount, the communication cost, and the operation cost.

Abstract: Each of a plurality of processors enters, to a model representing a neural network and including a common first weight, first data different from that used by the other processors, calculates an error gradient for the first weight, and integrates the gradients calculated by each processor. Each processor stores the first weight in a memory and updates the weight of the model to a second weight based on a hyperparameter value different from those used by the other processors, the integrated error gradient, and the first weight. Each processor enters common second data to the model, compares the evaluation results acquired by each processor, and selects a common hyperparameter value. Each processor updates the weight of the model to a third weight based on the selected hyperparameter value, the integrated error gradient, and the first weight stored in the memory.

Abstract: A method of controlling an information processing apparatus, the information processing apparatus being configured to perform learning processing by using a neural network, the method includes: executing a calculation processing that includes calculating a learning rate, the learning rate being configured to change in the form of a continuous curve such that the time from when the learning rate is at an intermediate value of a maximum value to when the learning rate reaches a minimum value is shorter than the time from when the learning processing starts to when the learning rate reaches the intermediate value of the maximum value; and executing a control processing that includes controlling, based on the calculated learning rate, an amount of update at the time when a weight parameter is updated in an update processing.

Abstract: Each of a plurality of processors enters, to a model representing a neural network and including a common first weight, first data different from that used by the other processors, calculates an error gradient for the first weight, and integrates the gradients calculated by each processor. Each processor stores the first weight in a memory and updates the weight of the model to a second weight based on a hyperparameter value different from those used by the other processors, the integrated error gradient, and the first weight. Each processor enters common second data to the model, compares the evaluation results acquired by each processor, and selects a common hyperparameter value. Each processor updates the weight of the model to a third weight based on the selected hyperparameter value, the integrated error gradient, and the first weight stored in the memory.

Abstract: A method of controlling an information processing apparatus, the information processing apparatus being configured to perform learning processing by using a neural network, the method includes: executing a calculation processing that includes calculating a learning rate, the learning rate being configured to change in the form of a continuous curve such that the time from when the learning rate is at an intermediate value of a maximum value to when the learning rate reaches a minimum value is shorter than the time from when the learning processing starts to when the learning rate reaches the intermediate value of the maximum value; and executing a control processing that includes controlling, based on the calculated learning rate, an amount of update at the time when a weight parameter is updated in an update processing.

Abstract: The number of non-zero elements is counted for each first row in a first matrix, and the maximum value therefor is determined. Pairs each containing the value and column identifier of a non-zero element are extracted from each first row, and dummy pairs are added for each first row that contains fewer non-zero elements than the maximum value, to generate compressed storage data including the same number of pairs for each first row. A second row with a row identifier corresponding to the column identifier included in each pair is extracted from a second matrix and is multiplied by the value included in the pair, to generate a row vector. By assigning an equal number of threads to each first row and summing row vectors corresponding to each first row using the assigned threads, a third matrix representing matrix multiplication between the first and second matrices is produced.

Abstract: An apparatus serves as at least one of a plurality of information processing devices each including a group of arithmetic processors, where the plurality of information processing devices are configured to perform parallel processing by using calculation result data of the groups of arithmetic processors included in the plurality of information processing devices. The apparatus includes a memory configured to store bandwidth information indicating a communication bandwidth with which an arithmetic processor included in the groups of arithmetic processors communicate with another arithmetic processor included in the groups of arithmetic processors. For a source arithmetic processor that is any one of the groups of arithmetic processors, the apparatus determines a destination arithmetic processor that is one of the groups of arithmetic processors to which the calculation result data of the source arithmetic processor is to be transferred, based on the bandwidth information stored in the memory.

Abstract: A machine learning method, using a neural network as a model, executed by a computer, the machine learning method including dividing a first batch data into a plurality of pieces of second batch data, the first batch data being a set of sample data to be input into the model in a machine learning, allocating the plurality of pieces of second batch data to a plurality of computers, the model having a specified layered structure and a specified parameter of the neural network being applied to the plurality of computers, making the plurality of computers to execute the machine learning based on the plurality of allocated second batch data, obtaining, from each of the plurality of computers, a plurality of correction amounts of the parameter derived by the executed machine learning, and correcting the model by modifying the specified parameter in accordance with the plurality of correction amounts.

Abstract: The parallel information processing apparatus includes a plurality of nodes each including a first processor and a second processor. The first processor is configured to execute a computation process using a coefficient for a target data, computing a coefficient variation based on a result of the computation process, transferring the computed coefficient variation to the second processor and requesting the second processor to execute a transfer/receipt process. The second processor is configured to transmit the coefficient variation transferred from the first processor to another node and receive the coefficient variation computed by another node and integrate the coefficient variation transferred from the first processor and the coefficient variation computed by another node. At least one of the first processor and the second processor updates the coefficient to be used for the computation process from next time onward based on the integrated coefficient variation.

Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Abstract: A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.

Abstract: In a semiconductor apparatus of the present invention, a plurality of circuit components are provided. A first bus interconnects the circuit components. A second bus interconnects the circuit components. A switching unit outputs a select signal that causes each circuit component to select one of the first bus and the second bus when transmitting a signal from one of the circuit components to another. The second bus has a size larger than a size of the first bus.

Abstract: A delay circuit that can prevent an increase in the scale of circuits. A data delay section included in the delay circuit delays input data by a plurality of data delay elements. A validity information delay section included in the delay circuit delays input validity information which indicates that the input data is valid by a plurality of validity information delay elements corresponding to the plurality of data delay elements included in the data delay section. As a result, the input data and the input validity information pass through a data delay element and a validity information delay element, respectively, which are associated with each other at the same timing. An output signal outputted from each data delay element can be taken out. Similarly, an output signal outputted from each validity information delay element can be taken out. Therefore, a plurality of output signals having desired delay amounts can be obtained for one input signal inputted to a delay circuit.

Abstract: An object of the invention is to improve a defect caused at the time of starting a midpoint potential generating circuit for use in a semiconductor device. A bias generating circuit supplies a grounding potential as a bias voltage Vbias and sets a midpoint potential of capacitors C1 and C2 to a grounding potential when a supply voltage VDD is lower than a first reference voltage. When the supply voltage VDD is equal to or higher than the first reference voltage, the bias generating circuit supplies the supply voltage VDD as the bias voltage Vbias. When the bias voltage Vbias is equal to or higher than a second reference voltage, the bias generating circuit supplies a voltage obtained by dividing the supply voltage VPP of the booster power supply circuit as the bias voltage Vbias to a node of the capacitors C1 and C2.