Patents by Inventor Masahiko Matsumoto
Masahiko Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922902Abstract: An image processor of a display device includes: an image sticking object detector which classifies a class of an input image data and outputs inference data including image sticking object information based on the classified class; a memory which stores previous inference data; a post-processor which calculates accumulative inference data, based on the inference data and the previous inference data received from the memory and generates corrected inference data, based on the accumulative inference data; and an image sticking prevention part which outputs an image data subjected to an image sticking prevention process, based on the corrected inference data.Type: GrantFiled: August 18, 2021Date of Patent: March 5, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Satoshi Uchino, Kazuhiro Matsumoto, Masahiko Takiguchi, Yasuhiko Shinkaji
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Patent number: 11139111Abstract: According to one embodiment, an inductive coupling system includes a first inductor and a second inductor. The first inductor includes a first wiring pattern provided on a first board and shaped as an open loop. The second inductor includes a second wiring pattern provided on a second board and shaped as an open loop. The second inductor is inductively coupled to the first inductor. A width of the second wiring pattern is narrower than a width of the first wiring pattern.Type: GrantFiled: January 17, 2019Date of Patent: October 5, 2021Assignee: Kabushiki Kaisha ToshibaInventor: Masahiko Matsumoto
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Publication number: 20190148064Abstract: According to one embodiment, an inductive coupling system includes a first inductor and a second inductor. The first inductor includes a first wiring pattern provided on a first board and shaped as an open loop. The second inductor includes a second wiring pattern provided on a second board and shaped as an open loop. The second inductor is inductively coupled to the first inductor. A width of the second wiring pattern is narrower than a width of the first wiring pattern.Type: ApplicationFiled: January 17, 2019Publication date: May 16, 2019Inventor: Masahiko Matsumoto
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Patent number: 10224146Abstract: According to one embodiment, an inductive coupling system includes a first inductor and a second inductor. The first inductor includes a first wiring pattern provided on a first board and shaped as an open loop. The second inductor includes a second wiring pattern provided on a second board and shaped as an open loop. The second inductor is inductively coupled to the first inductor. A width of the second wiring pattern is narrower than a width of the first wiring pattern.Type: GrantFiled: September 9, 2016Date of Patent: March 5, 2019Assignee: Kabushiki Kaisha ToshibaInventor: Masahiko Matsumoto
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Publication number: 20170117092Abstract: According to one embodiment, an inductive coupling system includes a first inductor and a second inductor. The first inductor includes a first wiring pattern provided on a first board and shaped as an open loop. The second inductor includes a second wiring pattern provided on a second board and shaped as an open loop. The second inductor is inductively coupled to the first inductor. A width of the second wiring pattern is narrower than a width of the first wiring pattern.Type: ApplicationFiled: September 9, 2016Publication date: April 27, 2017Inventor: Masahiko Matsumoto
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Patent number: 6998663Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.Type: GrantFiled: February 4, 2004Date of Patent: February 14, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masahiko Matsumoto
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Patent number: 6983402Abstract: In a computer device, a latch circuit latches a program read from a ROM. Even when a program C is mistakenly read from the ROM in place of a correct program B, a CPU outputs an access signal to the ROM again to read the program B at the same address from the ROM, and a match detection circuit compares the program B with the program C output from the latch circuit. Since these programs fail to match with each other, the CPU outputs the access signal again. If the ROM outputs the program B correctly this time, the program B matches with the program B output from the latch circuit when the match detection circuit compares these programs. The CPU then executes the program B as correctly read ROM data. Thus, even when a program in the ROM is mistakenly read, safe operation by a correctly read program is ensured.Type: GrantFiled: December 10, 2001Date of Patent: January 3, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Yoneda, Masahiko Matsumoto
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Publication number: 20040155273Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.Type: ApplicationFiled: February 4, 2004Publication date: August 12, 2004Inventors: Takashi Yoshitomi, Masahiko Matsumoto
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Patent number: 6746929Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.Type: GrantFiled: October 3, 2002Date of Patent: June 8, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masahiko Matsumoto
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Patent number: 6721903Abstract: An inventive information processor performs a predetermined process substantially continuously without causing runaway in its CPU even if extraneous noise has entered the power supply terminal thereof. When the incoming noise reaches relatively low Level 1(L), important information, determining the state of the CPU, is protected by saving it on a register. Thereafter, when the noise level exceeds Level 1(H), important information, representing the status of the predetermined process, is protected by storing it on a memory. Subsequently, when the noise level reaches Level 2, the CPU is suspended. And when the noise has decreased to less than Level 1(L), the predetermined process is resumed in accordance with the information saved and protected on the register and memory. Accordingly, even if noise has entered, the predetermined process can be continued without causing runway in the CPU after having been suspended for a while.Type: GrantFiled: February 8, 2001Date of Patent: April 13, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shiro Yoshioka, Masahiko Matsumoto, Shigenori Satoh
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Patent number: 6682967Abstract: A semiconductor device comprises a semiconductor substrate, a p-type well formed in the semiconductor substrate, an n-type well formed in the semiconductor substrate and positioned contiguous to the p-type well, an n-type diffused region formed in the p-type well, and a p-type diffused region formed in the n-type well, wherein a corner C1 having the p-type well on the inside is present in a part of the boundary pattern between the p-type well and the n-type well. At least one of the two sides defining the corner C1 extends from a top of the corner to the n-well by a predetermined width d over a predetermined length. The particular structure permits suppressing generation of a difference in a well isolation punch-through voltage between the corner and the straight portion of the well boundary of the semiconductor device, making it possible to provide a fine device structure while ensuring a desired well isolation punch-through voltage without relaxing a design rule.Type: GrantFiled: April 23, 2002Date of Patent: January 27, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Matsumoto, Hirofumi Igarashi
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Publication number: 20030102530Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same.Type: ApplicationFiled: January 6, 2003Publication date: June 5, 2003Applicant: Kabushiki Kaisha Toshiba.Inventors: Masahiko Matsumoto, Hisato Oyamatsu, Takeo Nakayama, Yasuhiro Fukaura, Kunihiro Kasai, Masahiro Inohara
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Publication number: 20030042521Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.Type: ApplicationFiled: October 3, 2002Publication date: March 6, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masahiko Matsumoto
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Patent number: 6525402Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same. In the present invention, a protection insulating film for preventing Cu from diffusing into the inside of the wafer is formed on a peripheral portion of a principal plane, a external side plane and a rear plane of the wafer. With this protection insulating film, the diffusion of Cu that is a wiring material into a chip formation region of the wafer is prevented, so that the variations of the transistor characteristic.Type: GrantFiled: September 14, 1999Date of Patent: February 25, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Matsumoto, Hisato Oyamatsu, Takeo Nakayama, Yasuhiro Fukaura, Kunihiro Kasai, Masahiro Inohara
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Publication number: 20030006465Abstract: A semiconductor device comprises a semiconductor substrate, a p-type well formed in the semiconductor substrate, an n-type well formed in the semiconductor substrate and positioned contiguous to the p-type well, an n-type diffused region formed in the p-type well, and a p-type diffused region formed in the n-type well, wherein a corner C1 having the p-type well on the inside is present in a part of the boundary pattern between the p-type well and the n-type well. At least one of the two sides defining the corner C1 extends from a top of the corner to the n-well by a predetermined width d over a predetermined length. The particular structure permits suppressing generation of a difference in a well isolation punch-through voltage between the corner and the straight portion of the well boundary of the semiconductor device, making it possible to provide a fine device structure while ensuring a desired well isolation punch-through voltage without relaxing a design rule.Type: ApplicationFiled: April 23, 2002Publication date: January 9, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Masahiko Matsumoto, Hirofumi Igarashi
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Publication number: 20020073286Abstract: In a computer device, a latch circuit latches a program read from a ROM. Even when a program C is mistakenly read from the ROM in place of a correct program B, a CPU outputs an access signal to the ROM again to read the program B at the same address from the ROM, and a match detection circuit compares the program B with the program C output from the latch circuit. Since these programs fail to match with each other, the CPU outputs the access signal again. If the ROM outputs the program B correctly this time, the program B matches with the program B output from the latch circuit when the match detection circuit compares these programs. The CPU then executes the program B as correctly read ROM data. Thus, even when a program in the ROM is mistakenly read, safe operation by a correctly read program is ensured.Type: ApplicationFiled: December 10, 2001Publication date: June 13, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Takashi Yoneda, Masahiko Matsumoto
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Patent number: 6399992Abstract: A semiconductor device comprises a semiconductor substrate, a p-type well formed in the semiconductor substrate, an n-type well formed in the semiconductor substrate and positioned contiguous to the p-type well, an n-type diffused region formed in the p-type well, and a p-type diffused region formed in the n-type well, wherein a corner C1 having the p-type well on the inside is present in a part of the boundary pattern between the p-type well and the n-type well. At least one of the two sides defining the corner C1 extends from a top of the corner to the n-well by a predetermined width d over a predetermined length. The particular structure permits suppressing generation of a difference in a well isolation punch-through voltage between the corner and the straight portion of the well boundary of the semiconductor device, making it possible to provide a fine device structure while ensuring a desired well isolation punch-through voltage without relaxing a design rule.Type: GrantFiled: March 29, 2001Date of Patent: June 4, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Masahiko Matsumoto, Hirofumi Igarashi
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Publication number: 20010026003Abstract: A semiconductor device, comprising a first wiring formed in a first insulating film, a second insulating film formed on the first insulating film, a first electrode film selectively formed on the second insulating film, a third insulating film formed on the first electrode film, and having an end portion and a central portion, wherein the end portion has a thickness thinner than the central portion, a second electrode film formed on the central portion of the third insulating film such that the second electrode film faces the first electrode film.Type: ApplicationFiled: March 22, 2001Publication date: October 4, 2001Inventors: Takashi Yoshitomi, Masahiko Matsumoto
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Publication number: 20010018752Abstract: An inventive information processor performs a predetermined process substantially continuously without causing runaway in its CPU even if extraneous noise has entered the power supply terminal thereof. When the incoming noise reaches relatively low Level 1(L), important information, determining the state of the CPU, is protected by saving it on a register. Thereafter, when the noise level exceeds Level 1(H), important information, representing the status of the predetermined process, is protected by storing it on a memory. Subsequently, when the noise level reaches Level 2, the CPU is suspended. And when the noise has decreased to less than Level 1(L), the predetermined process is resumed in accordance with the information saved and protected on the register and memory. Accordingly, even if noise has entered, the predetermined process can be continued without causing runway in the CPU after having been suspended for a while.Type: ApplicationFiled: February 8, 2001Publication date: August 30, 2001Applicant: Matsushita Electric Industrial Co., LtdInventors: Shiro Yoshioka, Masahiko Matsumoto, Shigenori Satoh
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Patent number: 6253305Abstract: A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.Type: GrantFiled: January 7, 1999Date of Patent: June 26, 2001Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshimichi Matsuzaki, Masashi Deguchi, Toshifumi Hamaguchi, Yutaka Tanase, Masahiko Matsumoto