Patents by Inventor Masahiko Suzuki
Masahiko Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210036158Abstract: A semiconductor device (100) includes a TFT (10) supported on a substrate (11), wherein the TFT (10) includes a gate electrode (12g), a gate insulating layer (14) that covers the gate electrode (12g), and an oxide semiconductor layer (16) that is formed on the gate insulating layer (14). The oxide semiconductor layer 16 has a layered structure including a first oxide semiconductor layer (16a) in contact with the gate insulating layer (14) and a second oxide semiconductor layer (16b) layered on the first oxide semiconductor layer (16a). The first oxide semiconductor layer (16a) and the second oxide semiconductor layer (16b) both include In, Ga and Zn; an In atomic ratio of the first oxide semiconductor layer (16a) is greater than a Zn atomic ratio thereof, and an In atomic ratio of the second oxide semi-conductor layer (16b) is smaller than a Zn atomic ratio thereof; and the oxide semiconductor layer (16) has a side surface of a forward tapered shape.Type: ApplicationFiled: March 8, 2018Publication date: February 4, 2021Inventors: Setsuji NISHIMIYA, Tohru DAITOH, Masahiko SUZUKI, Kengo HARA, Hajime IMAI, Toshikatsu ITOH, Hideki KITAGAWA, Tetsuo KIKUCHI, Teruyuki UEDA
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Publication number: 20210013238Abstract: An active matrix substrate includes a substrate; a plurality of gate bus lines and a plurality of source bus lines; an oxide semiconductor TFT that includes an oxide semiconductor layer, a gate insulating layer, and a gate electrode; a pixel electrode; and an upper insulating layer. The oxide semiconductor layer includes a high resistance region, and a first region and a second region. The high resistance region includes a channel region, a first channel offset region, and a second channel offset region. The upper insulating layer is disposed so as to overlap the channel region, the first channel offset region, and the second channel offset region, and so as not to overlap any of the first region and the second region, when viewed from the normal direction of the main surface of the substrate.Type: ApplicationFiled: July 2, 2020Publication date: January 14, 2021Inventors: Masahiko SUZUKI, Yoshihito HARA, Tetsuo KIKUCHI, Setsuji NISHIMIYA, Kengo HARA, Masamitsu YAMANAKA, Hitoshi TAKAHATA, Hajime IMAI, Tohru DAITOH
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Publication number: 20200388637Abstract: An active matrix substrate includes a substrate, a plurality of oxide semiconductor TFTs, a plurality of gate bus lines, a plurality of source bus lines, and at least one trunk wiring provided in a non-display region and transmitting a signal, and a plurality of other wirings, each of which is disposed so as to at least partially overlap the trunk wirings. The active matrix substrate includes a first metal layer, a second metal layer disposed above the first metal layer, and a third metal layer disposed above the second metal layer on the substrate. One of the first, second, and third metal layers includes a source bus line, and other layer includes a gate bus line. The trunk wiring is formed in two metal layer of the first, second and third metal layers.Type: ApplicationFiled: June 4, 2020Publication date: December 10, 2020Inventors: Tetsuo KIKUCHI, Tohru DAITOH, Hajime IMAI, Masahiko SUZUKI, Setsuji NISHIMIYA, Kengo HARA, Masamitsu YAMANAKA, Hitoshi TAKAHATA
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Publication number: 20200368098Abstract: A processing unit includes a direction decision unit and a guide information generation unit. The direction decision unit decides a direction in which a person who behaves without a sense of sight walks. The guide information generation unit generates guide information for the person who behaves without the sense of sight to walk in the decided direction. The present technology is applicable, for example, to a smartphone or the like used by the person who behaves without the sense of sight.Type: ApplicationFiled: August 10, 2020Publication date: November 26, 2020Inventors: KUMI YASHIRO, TETSUYA NARUSE, JUNICHI KOSAKA, YASUMASA SUZUKI, HIROKO NISHIOKA, HITOSHI RIKUKAWA, KOHEI TAKADA, MASAHIKO SUZUKI
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Patent number: 10825843Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode.Type: GrantFiled: October 12, 2017Date of Patent: November 3, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Teruyuki Ueda, Hideki Kitagawa, Tohru Daitoh, Hajime Imai, Masahiko Suzuki, Setsuji Nishimiya, Tetsuo Kikuchi, Toshikatsu Itoh, Kengo Hara
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Patent number: 10818697Abstract: A semiconductor device includes a first TFT, a first source-side connection section that is formed from a part of a second metal film and connected to a first source region, a first drain-side connection section that is formed from a part of the second metal film and connected to a first drain region, a second TFT that is driven by the first TFT, a second source-side connection section that is formed from a part of a first metal film and connected to a second source region, and a second drain-side connection section that is formed from a part of the first metal film or a second transparent electrode film and connected to a second drain region.Type: GrantFiled: July 18, 2019Date of Patent: October 27, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Masahiko Suzuki, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Setsuji Nishimiya, Teruyuki Ueda, Masamitsu Yamanaka, Kengo Hara
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Patent number: 10818766Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.Type: GrantFiled: March 23, 2018Date of Patent: October 27, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Masahiko Suzuki, Hideki Kitagawa, Tetsuo Kikuchi, Toshikatsu Itoh, Setsuji Nishimiya, Teruyuki Ueda, Kengo Hara, Hajime Imai, Tohru Daitoh
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Patent number: 10816865Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).Type: GrantFiled: March 13, 2017Date of Patent: October 27, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Tohru Daitoh, Hajime Imai, Toshikatsu Itoh, Hisao Ochi, Hideki Kitagawa, Masahiko Suzuki, Teruyuki Ueda, Ryosuke Gunji, Kengo Hara, Setsuji Nishimiya
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Patent number: 10797082Abstract: A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.Type: GrantFiled: September 17, 2018Date of Patent: October 6, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Tohru Daitoh, Hajime Imai, Masahiko Suzuki, Setsuji Nishimiya, Teruyuki Ueda, Kengo Hara
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Publication number: 20200312885Abstract: The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.Type: ApplicationFiled: March 26, 2020Publication date: October 1, 2020Inventors: Hajime IMAI, Tohru DAITOH, Tetsuo KIKUCHI, Masamitsu YAMANAKA, Yoshihito HARA, Tatsuya KAWASAKI, Masahiko SUZUKI, Setsuji NISHIMIYA
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Publication number: 20200303425Abstract: A method for manufacturing an active matrix board includes (E) a step of forming a source contact hole and a drain contact hole in an interlayer insulating layer such that a portion of a source contact region of an oxide semiconductor layer and a portion of a drain contact region thereof are exposed and forming a connecting portion contact hole in the interlayer insulating layer and a lower insulating layer such that a portion of a lower conductive layer is exposed; and (F) a step of forming a source electrode, a drain electrode, and an upper conductive layer on the interlayer insulating layer; and the step (E) includes (e-1) a step of forming a photoresist film on the interlayer insulating layer and (e-2) a step of forming a photoresist layer in such a manner that the photoresist film is exposed to light using a multi-tone mask and is then developed.Type: ApplicationFiled: March 17, 2020Publication date: September 24, 2020Inventors: Kengo HARA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Masamitsu YAMANAKA, Teruyuki UEDA, Hitoshi TAKAHATA
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Publication number: 20200287054Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer positioned between the semiconductor layer and the gate electrode, and a source electrode and a drain electrode that are electrically connected to the semiconductor layer, wherein the semiconductor layer has a stacked layer structure including a first oxide semiconductor layer including In, Ga, Zn, and Sn, and a second oxide semiconductor layer including In, Ga, Zn, and Sn, having a lower mobility than the first oxide semiconductor layer, and disposed on the first oxide semiconductor layer so as to be in direct contact with the first oxide semiconductor layer, the first and the second oxide semiconductor layers are amorphous, and a Sn atomic ratio R1 relative to all metal elements in the first oxide semiconductor layer and a Sn atomic ratio R2 relative to all metal elements in the second oxide semiconductor layer satisfy 0.8×R1?R2?1.2×R1.Type: ApplicationFiled: March 4, 2020Publication date: September 10, 2020Inventors: Masahiko SUZUKI, Hajime IMAI, Tetsuo KIKUCHI, Yoshimasa CHIKAMA, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA, Kengo HARA, Hitoshi TAKAHATA, Tohru DAITOH
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Patent number: 10765588Abstract: There is provided a processing unit that includes a direction decision unit and a guide information generation unit. The direction decision unit determines a direction in which a person who behaves without a sense of sight walks. The guide information generation unit generates guide information for the person who behaves without the sense of sight to walk in the determined direction. The present technology is applicable, for example, to a smartphone or the like used by the person who behaves without the sense of sight.Type: GrantFiled: June 23, 2017Date of Patent: September 8, 2020Assignees: SONY CORPORATION, SONY MOBILE COMMUNICATIONS INC.Inventors: Kumi Yashiro, Tetsuya Naruse, Junichi Kosaka, Yasumasa Suzuki, Hiroko Nishioka, Hitoshi Rikukawa, Kohei Takada, Masahiko Suzuki
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Publication number: 20200264485Abstract: An active matrix substrate 10 includes: switching elements 120 that are connected with gate lines and data lines provided on a substrate; pixel electrodes 130 that are connected with the switching elements 120; counter electrodes 140 that overlap with the pixel electrodes 130 when viewed in a plan view; a flattening film 154; and lines 142. The flattening film 154 covers the switching elements 120, and first contact holes CH1 that pass through the flattening film 154 are formed at positions that overlap with the lines 142 when viewed in a plan view. The pixel electrodes 130 and the counter electrodes 140 are arranged so that each of the same partially covers the flattening film 154. The line 142 and the counter electrode 140 are connected with each other in the first contact hole CH1.Type: ApplicationFiled: February 12, 2020Publication date: August 20, 2020Inventors: Setsuji NISHIMIYA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Masahiko SUZUKI, Teruyuki UEDA, Masamitsu YAMANAKA, Kengo HARA, Hitoshi TAKAHATA
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Patent number: 10748939Abstract: A semiconductor device (100A) is provided with: a gate electrode (3); an oxide semiconductor layer (5); a thin-film transistor (101) including a gate insulating layer (4), a source electrode (7S), and a drain electrode (7D); an inter-layer insulating layer (11) arranged so as to cover the thin-film transistor (101) and come into contact with a channel area (5c) of the thin-film transistor (101); and a transparent electroconductive layer (19) arranged on the inter-layer insulating layer (11), the source electrode (7S) and the drain electrode (7D) each having a copper layer (7a), and the device being further provided with a copper oxide film (8) arranged between the source and drain electrodes and the inter-layer insulating layer (11). The inter-layer insulating layer (11) covers the drain electrode (7D) with the copper oxide film (8) interposed therebetween.Type: GrantFiled: December 6, 2018Date of Patent: August 18, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Hideki Kitagawa, Tohru Daitoh, Hajime Imai, Hisao Ochi, Tetsuo Fujita, Tetsuo Kikuchi, Shingo Kawashima, Masahiko Suzuki
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Patent number: 10741696Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer isType: GrantFiled: September 21, 2017Date of Patent: August 11, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Masahiko Suzuki, Hajime Imai, Hideki Kitagawa, Tetsuo Kikuchi, Setsuji Nishimiya, Teruyuki Ueda, Kengo Hara, Tohru Daitoh, Toshikatsu Itoh
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Publication number: 20200227560Abstract: A semiconductor device (100) of an embodiment of the present invention includes: a substrate (1); a plurality of TFTs (10) supported by the substrate; and a protecting layer (20) covering the plurality of TFTs. Each of the TFTs is a back channel etch type TFT which includes a gate electrode (2), a gate insulating layer (3), an oxide semiconductor layer (4), a source electrode (5) and a drain electrode (6). The gate electrode includes a tapered portion (TP) defined by a lateral surface (2s) which has a tapered shape. When viewed in a direction normal to a substrate surface, a periphery of the oxide semiconductor layer includes an edge (4e1, 4e2) which extends in a direction intersecting a channel width direction (DW) and which is more internal than an edge of the gate electrode in the channel width direction. The distance from the edge of the oxide semiconductor layer to an inside end of the tapered portion is not less than 1.5 ?m.Type: ApplicationFiled: March 1, 2018Publication date: July 16, 2020Inventors: Toshikatsu ITOH, Hajime IMAI, Hideki KITAGAWA, Tetsuo KIKUCHI, Setsuji NISHIMIYA, Teruyuki UEDA, Kengo HARA, Tohru DAITOH, Masahiko SUZUKI
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Patent number: 10700210Abstract: A semiconductor device includes a substrate and a thin film transistor supported by the substrate. The thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and source and drain electrodes electrically connected to the oxide semiconductor layer. The gate insulating layer includes a first portion which is covered with the oxide semiconductor layer and a second portion which is adjacent to the first portion and which is not covered with any of the oxide semiconductor layer, the source electrode and the drain electrode. The second portion is smaller in thickness than the first portion, and the difference in thickness between the second portion and the first portion is more than 0 nm and not more than 50 nm.Type: GrantFiled: November 19, 2015Date of Patent: June 30, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hajime Imai, Hisao Ochi, Tetsuo Fujita, Hideki Kitagawa, Masahiko Suzuki, Shingo Kawashima, Tohru Daitoh
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Publication number: 20200183208Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).Type: ApplicationFiled: March 13, 2017Publication date: June 11, 2020Inventors: Tetsuo KIKUCHI, Tohru DAITOH, Hajime IMAI, Toshikatsu ITOH, Hisao OCHI, Hideki KITAGAWA, Masahiko SUZUKI, Teruyuki UEDA, Ryosuke GUNJI, Kengo HARA, Setsuji NISHIMIYA
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Publication number: 20200185425Abstract: Each of pixel regions of an active matrix substrate (1002) includes: a lower insulating layer (5); an oxide semiconductor layer (7) that is arranged on the lower insulating layer and includes an active region (7a) of an oxide semiconductor TFT; an upper insulating layer (9) that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer (10) that is arranged on the upper insulating layer and includes an upper gate electrode (10a) and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layer 7 further includes an extension region (7e) that extends from the active region (7a) in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region (7e) is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer (9) interpType: ApplicationFiled: May 11, 2018Publication date: June 11, 2020Inventors: Kengo HARA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Hideki KITAGAWA, Teruyuki UEDA, Masahiko SUZUKI, Setsuji NISHIMIYA, Toshikatsu ITOH