Patents by Inventor Masahiko Suzuki

Masahiko Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10662917
    Abstract: The present invention relates to a water turbine in which a unit pipe can be joined by an optional number and a rotating shaft integrated with a rotor can be joined by an optional number according to intended use or condition of use, and by which each rotor can be supported stably.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: May 26, 2020
    Assignee: NTN Corporation
    Inventor: Masahiko Suzuki
  • Publication number: 20200150472
    Abstract: A substrate includes thin film transistors, each of which includes: an upper gate electrode formed of a first conductive film and continuous with one of gate lines; a source electrode formed of a second conductive film and continuous with one of source lines; a channel region formed of a portion of a semiconductor film over which an upper gate insulating film is disposed and overlapping the upper gate electrode; a source region formed of a portion of the semiconductor film and continuous with the channel region, and a drain region formed of a portion of the semiconductor film and continuous with the channel region on an opposite side of the channel region from the source region. The source electrode connects the source line and the source region through a first contact hole in an interlayer insulating film disposed over the first conductive film and containing a photosensitive material.
    Type: Application
    Filed: November 14, 2019
    Publication date: May 14, 2020
    Inventors: Tetsuo KIKUCHI, Tohru DAITOH, Hajime IMAI, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Kengo HARA, Masamitsu YAMANAKA, Hitoshi TAKAHATA
  • Patent number: 10641238
    Abstract: A water turbine device is provided which can move a water turbine from a use position to a nonuse position with a light force, and which has a simplified structure. An intermediate portion of a suspension support rod for suspending a water turbine immersed in a flowing water in a waterway is pivotally attached to a platform provided on the waterway with a horizontal shaft, and a power generation device as a balance weight is provided at the free end of the suspension support rod, and the water turbine is rotatable around the horizontal shaft between the use position where the water turbine is immersed in a flowing water and the nonuse position above the flowing water.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: May 5, 2020
    Assignee: NTN CORPORATION
    Inventor: Masahiko Suzuki
  • Publication number: 20200111433
    Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.
    Type: Application
    Filed: March 16, 2018
    Publication date: April 9, 2020
    Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
  • Patent number: 10593809
    Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 17, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiko Suzuki, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Setsuji Nishimiya, Teruyuki Ueda, Kengo Hara
  • Patent number: 10584674
    Abstract: A hydraulic power generating apparatus which can be easily disposed in a water channel, such as a waterway or a water conducting pipe. The hydraulic power generating apparatus comprises a horizontal rotor supporting housing (4) having a rotor, a holding body (5) erected on an upper surface of the rotor supporting housing (4), a support ring (2) in which the rotor supporting housing (4) is fixed, and a power generator (11). The rotor supporting housing (4) is integrally fixed within the support ring (2) by the holding body (5). The power generator (11) is disposed on the upper part of the holding body (5) protruding from the support ring (2), and the support ring (2) is formed with attachment portions (2A, 2B) for fixing the rotor supporting housing (4) in a water channel.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: March 10, 2020
    Assignee: NTN CORPORATION
    Inventor: Masahiko Suzuki
  • Publication number: 20200073189
    Abstract: [Object] To provide an active matrix substrate (1) that includes an organic insulating film (OIL) and first source layers (FSL2 to FSL4) and second source layers (SSL1 to SSL3), which constitute two-layer wiring lines, and that is produced with a high yield. [Solution] In an active matrix substrate (1), of the first source layers (FSL2 to FSL4) and the second source layers (SSL1 to SSL3), the second source layers (SSL1 to SSL3) arranged further from the substrate (2) are in contact with an organic insulating film (OIL) with a second inorganic insulating film (SINOIL) interposed therebetween.
    Type: Application
    Filed: August 23, 2019
    Publication date: March 5, 2020
    Inventors: Hitoshi TAKAHATA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Kengo HARA, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA, Yoshihito HARA
  • Publication number: 20200058678
    Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode.
    Type: Application
    Filed: October 12, 2017
    Publication date: February 20, 2020
    Inventors: Teruyuki UEDA, Hideki KITAGAWA, Tohru DAITOH, Hajime IMAI, Masahiko SUZUKI, Setsuji NISHIMIYA, Tetsuo KIKUCHI, Toshikatsu ITOH, Kengo HARA
  • Publication number: 20200043955
    Abstract: A semiconductor device includes a first TFT, a first source-side connection section that is formed from a part of a second metal film and connected to a first source region, a first drain-side connection section that is formed from a part of the second metal film and connected to a first drain region, a second TFT that is driven by the first TFT, a second source-side connection section that is formed from a part of a first metal film and connected to a second source region, and a second drain-side connection section that is formed from a part of the first metal film or a second transparent electrode film and connected to a second drain region.
    Type: Application
    Filed: July 18, 2019
    Publication date: February 6, 2020
    Inventors: Masahiko SUZUKI, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA, Kengo HARA
  • Publication number: 20200035717
    Abstract: A thin film transistor substrate includes a source line, a gate electrode, a channel region, a source region, a drain region, and a pixel electrode. The gate electrode is a portion of a first metal film disposed upper than a first insulating film that is disposed upper than a semiconductor film. The source line is a portion of a second metal film disposed upper than a second insulating film that is disposed upper than the first metal film. The channel region is a portion of a section of the semiconductor film and disposed to overlap the gate electrode. The source region is prepared by reducing a resistance of a section of the semiconductor film. The drain region is prepared by reducing a resistance of a section of the semiconductor film. The pixel electrode is prepared by reducing a resistance of a section of the semiconductor film.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 30, 2020
    Inventors: Kengo HARA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA
  • Publication number: 20200027958
    Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.
    Type: Application
    Filed: March 23, 2018
    Publication date: January 23, 2020
    Inventors: Masahiko SUZUKI, Hideki KITAGAWA, Tetsuo KIKUCHI, Toshikatsu ITOH, Setsuji NISHIMIYA, Teruyuki UEDA, Kengo HARA, Hajime IMAI, Tohru DAITOH
  • Publication number: 20200020756
    Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.
    Type: Application
    Filed: March 19, 2018
    Publication date: January 16, 2020
    Inventors: Teruyuki UEDA, Hideki KITAGAWA, Tohru DAITOH, Hajime IMAI, Masahiko SUZUKI, Setsuji NISHIMIYA, Tetsuo KIKUCHI, Toshikatsu ITOH, Kengo HARA
  • Publication number: 20190326443
    Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is
    Type: Application
    Filed: September 21, 2017
    Publication date: October 24, 2019
    Inventors: Masahiko SUZUKI, Hajime IMAI, Hideki KITAGAWA, Tetsuo KIKUCHI, Setsuji NISHIMIYA, Teruyuki UEDA, Kengo HARA, Tohru DAITOH, Toshikatsu ITOH
  • Publication number: 20190307632
    Abstract: [Object] To enable those who behave without the sense of sight to safely walk in a correct direction. [Solution] A processing unit includes a direction decision unit and a guide information generation unit. The direction decision unit decides a direction in which a person who behaves without a sense of sight walks. The guide information generation unit generates guide information for the person who behaves without the sense of sight to walk in the decided direction. The present technology is applicable, for example, to a smartphone or the like used by the person who behaves without the sense of sight.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 10, 2019
    Inventors: Kumi YASHIRO, Tetsuya NARUSE, Junichi KOSAKA, Yasumasa SUZUKI, Hiroko NISHIOKA, Hitoshi RIKUKAWA, Kohei TAKADA, Masahiko SUZUKI
  • Publication number: 20190275763
    Abstract: A release sheet for semiconductor compression molding includes a release layer that includes particles, and a base layer. The content ratio of the particles in the release layer is from 5% by volume to 65% by volume.
    Type: Application
    Filed: May 20, 2016
    Publication date: September 12, 2019
    Inventors: Masahiko SUZUKI, Ryo TAMURA, Takuji IKEYA
  • Publication number: 20190280126
    Abstract: A semiconductor device includes a thin film transistor, wherein: a semiconductor layer of the thin film transistor has a layered structure including a lower oxide semiconductor layer including In, Ga, Zn and Sn and an upper oxide semiconductor layer arranged on the lower oxide semiconductor layer and including In, Ga and Zn; a thickness of the lower oxide semiconductor layer is 20 nm or less; an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer is 5% or more; the upper oxide semiconductor layer includes no Sn, or an atomic ratio of Sn with respect to all metal elements of the upper oxide semiconductor layer is smaller than an atomic ratio of Sn with respect to all metal elements of the lower oxide semiconductor layer; and a first angle ?1 between a side surface and a lower surface of the lower oxide semiconductor layer is smaller than a second angle ?2 between a side surface and a lower surface of the upper oxide semiconductor layer.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 12, 2019
    Inventors: Tetsuo KIKUCHI, Masahiko SUZUKI, Setsuji NISHIMIYA, Teruyuki UEDA, Masamitsu YAMANAKA, Tohru DAITOH, Hajime IMAI, Kengo HARA
  • Patent number: 10381487
    Abstract: A thin film transistor includes a channel section formed from semiconductor material, a source electrode connected to one end of the channel section, a drain electrode connected to another end of the channel section, an upper gate electrode included in an upper layer than the channel section and overlapping the channel section, a lower gate electrode included in a lower layer than the channel section and overlapping the channel section, an upper gate insulation film disposed between the upper gate electrode and the channel section, and a lower gate insulation film disposed between the lower gate electrode and the channel section and having a film thickness relatively greater than that of the upper gate insulation film.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Teruyuki Ueda
  • Publication number: 20190195187
    Abstract: A hydraulic turbine suspending device is provided which facilitates the positioning of a hydroelectric generator in a waterway, and which is easy to work on. The hydraulic turbine suspending device is a support that suspends a hydraulic turbine (10) in a waterway by laterally bridging the same, and comprises a combination of a suspending beam (2) positioned in parallel with the upstream and downstream sides of the waterway; a plurality of stanchions (5) that support the edges of the suspending beam (2) in a horizontal position on the outside of the waterway; and a floor plate (6) provided in a tensioned state to the suspending beam (2).
    Type: Application
    Filed: September 7, 2017
    Publication date: June 27, 2019
    Inventor: Masahiko SUZUKI
  • Patent number: 10332968
    Abstract: A semiconductor device (100) is provided with a thin film transistor including an oxide semiconductor layer (5), a gate electrode (3), a gate insulating layer (4), and a source electrode (7s) and a drain electrode (7d) that are in contact with the oxide semiconductor layer, at least one electrode of the source electrode (7s), the drain electrode (7d), and the gate electrode (3) has a multilayer structure that includes a first layer (3A, 7A) containing copper and a second layer (3B, 7B) containing titanium or molybdenum, the thickness of the first layer (3A, 7A) is more than the thickness of the second layer (3B, 7B), when the source electrode (7s) or the drain electrode (7d) has the multilayer structure, the second layer is arranged on the oxide semiconductor layer side of the first layer so as to be in contact with the surface of the oxide semiconductor layer (5), when the gate electrode (3) has the multilayer structure, the second layer is arranged on the substrate (1) side of the first layer, and the thick
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: June 25, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Fujita, Hajime Imai, Hisao Ochi, Tetsuo Kikuchi, Hideki Kitagawa, Masahiko Suzuki, Shingo Kawashima, Tohru Daitoh
  • Publication number: 20190148558
    Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT including an oxide semiconductor layer supported by the substrate and having a multilayer structure including a protective oxide semiconductor layer and a channel oxide semiconductor layer disposed closer to the substrate than the protective oxide semiconductor layer, an upper insulating layer on the oxide semiconductor layer, an upper gate electrode disposed on the upper insulating layer, an interlayer insulating layer covering the oxide semiconductor layer and the upper gate electrode, and first and second electrodes electrically connected to the oxide semiconductor layer, wherein a first opening extends through at least the interlayer insulating layer and the protective oxide semiconductor layer, and exposes a portion of the channel oxide semiconductor layer, and the first electrode is disposed on the interlayer insulating layer and within the first opening, and is in direct contact with, within the first opening, the portion.
    Type: Application
    Filed: November 7, 2018
    Publication date: May 16, 2019
    Inventors: Masahiko SUZUKI, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Setsuji NISHIMIYA, Teruyuki UEDA, Kengo HARA