Abstract: Disclosed is a brushless motor (1A) which is an axial gap type brushless motor (1A) wherein stators (3A, 4A) comprising a coil (41) and a rotor (2) comprising a permanent magnet (23) are arranged with a gap therebetween in the axial direction. The coil (41) is a band-like wire which is spirally wound such that the width direction of the band-like wire generally coincides with the direction of the magnetic flux that is generated by the permanent magnet (23) of the rotor (2). Consequently, the axial gap type brushless motor (1A) having the above-described structure can be further reduced in eddy current loss in comparison to conventional brushless motors.

Abstract: Disclosed is a brushless motor (1A) which is an axial gap type brushless motor (1A) wherein stators (3A, 4A) comprising a coil (41) and a rotor (2) comprising a permanent magnet (23) are arranged with a gap therebetween in the axial direction. The coil (41) is a band-like wire which is spirally wound such that the width direction of the band-like wire generally coincides with the direction of the magnetic flux that is generated by the permanent magnet (23) of the rotor (2). Consequently, the axial gap type brushless motor (1A) having the above-described structure can be further reduced in eddy current loss in comparison to conventional brushless motors.

Abstract: A method for manufacturing a porous dielectric substrate including patterned electrodes includes a patterned electrode-forming step of preparing a support plate having a releasable flat face and then forming the patterned electrodes on the flat face, a porous dielectric substrate-forming step of feeding a material for forming the porous dielectric substrate onto the flat face having the patterned electrodes arranged thereon to form the porous dielectric substrate in which the patterned electrodes are embedded, and a separation step of separating the support plate from the porous dielectric substrate having the patterned electrodes embedded therein. In the patterned electrode-forming step, the patterned electrodes formed on the flat face are processed to have rough surfaces in the patterned electrode-forming step. Alternatively, after the flat face is coated with a releasing agent, the patterned electrodes are formed on the resulting flat face.

Abstract: A dielectric line having a sufficient ensured strength and being suitable for mass production and a production method therefor are provided. The production method is a method for manufacturing a dielectric line having a dielectric strip which is provided between two conductive plates approximately parallel to each other and which has a width smaller than that of the conductive plates, and dielectric medium layers which are filled between the conductive plates other than the dielectric strip and which is composed of a porous material having a dielectric constant smaller than that of the dielectric strip.

Abstract: A dielectric line having a sufficient ensured strength and being suitable for mass production and a production method therefor are provided. The production method is a method for manufacturing a dielectric line having a dielectric strip which is provided between two conductive plates approximately parallel to each other and which has a width smaller than that of the conductive plates, and dielectric medium layers which are filled between the conductive plates other than the dielectric strip and which is composed of a porous material having a dielectric constant smaller than that of the dielectric strip.

Abstract: A feed antenna includes a pair of conductive members, a dielectric waveguide placed therebetween, a dielectric member that is placed between the conductive members and located close to the dielectric waveguide, and a plurality of dielectric binding sections for binding the dielectric waveguide to the dielectric member. One of the conductive members has a plurality of openings.

Abstract: A high-frequency micro-strip line for transmitting a high-frequency wave for a wireless LAN system has a layered structure where, on a ground layer made of a conductive material, a dielectric layer made of a dielectric material and a signal line made of a conductive material are successively laid. The high-frequency micro-strip line further includes a patch antenna comprising a dielectric plate made of a dielectric material and a patch made of a conductive material, which are successively laid into a layered structure, the patch antenna being electrically connected to the signal line. A wireless-communication RF signal transmission device capable of being applied to such a line is also provided.

Abstract: A method for manufacturing a porous dielectric substrate including patterned electrodes includes a patterned electrode-forming step of preparing a support plate having a releasable flat face and then forming the patterned electrodes on the flat face, a porous dielectric substrate-forming step of feeding a material for forming the porous dielectric substrate onto the flat face having the patterned electrodes arranged thereon to form the porous dielectric substrate in which the patterned electrodes are embedded, and a separation step of separating the support plate from the porous dielectric substrate having the patterned electrodes embedded therein. In the patterned electrode-forming step, the patterned electrodes formed on the flat face are processed to have rough surfaces in the patterned electrode-forming step. Alternatively, after the flat face is coated with a releasing agent, the patterned electrodes are formed on the resulting flat face.

Abstract: A dielectric line having a sufficient ensured strength and being suitable for mass production and a production method therefor are provided. The production method is a method for manufacturing a dielectric line having a dielectric strip which is provided between two conductive plates approximately parallel to each other and which has a width smaller than that of the conductive plates, and dielectric medium layers which are filled between the conductive plates other than the dielectric strip and which is composed of a porous material having a dielectric constant smaller than that of the dielectric strip.

Abstract: A feed antenna includes a pair of conductive members, a dielectric waveguide placed therebetween, a dielectric member that is placed between the conductive members and located close to the dielectric waveguide, and a plurality of dielectric binding sections for binding the dielectric waveguide to the dielectric member. One of the conductive members has a plurality of openings.

Abstract: A cryptographic processing apparatus for performing cryptographic processing using input data to generate output data is provided. The cryptographic processing apparatus includes a storage unit for storing chain data which is used for reflecting present cryptographic processing on next cryptographic processing, and for renewing the chain data each time cryptographic processing is performed, a merging unit for merging the chain data stored in the storage unit with the input data to generate merged data, and a main cryptographic processing unit for performing main cryptographic processing using the merged data to generate output data and for outputting intermediate data generated during a generation of the output data, wherein the storage unit renews the chain data by storing the intermediate data outputted by the main cryptographic processing unit as the new chain data, which is used for the next cryptographic processing.

Abstract: A cryptographic processing apparatus for performing cryptographic processing using input data to generate output data is provided. The cryptographic processing apparatus includes a storage unit for storing chain data which is used for reflecting present cryptographic processing on next cryptographic processing, and for renewing the chain data each time cryptographic processing is performed, a merging unit for merging the chain data stored in the storage unit with the input data to generate merged data, and a main cryptographic processing unit for performing main cryptographic processing using the merged data to generate output data and for outputting intermediate data generated during a generation of the output data, wherein the storage unit renews the chain data by storing the intermediate data outputted by the main cryptographic processing unit as the new chain data, which is used for the next cryptographic processing.

Abstract: A neural network circuit for performing a processing of recognizing voices, images and the like comprises a weight memory for holding a lot of weight values (initial weight values) which correspond to a plurality of input terminals of each of a plurality of neurons forming a neural network and have been initially learned, and a difference value memory for storing difference values between the weight values of the weight memory and additionally learned weight values. The weight memory is formed by a ROM. The difference value memory is formed by a SRAM, for example. During operation of recognizing input data, the initial weight values of the weight memory and the difference values of the difference value memory are added together. The added weight values are used to calculate an output value of each neuron of an output layer. Accordingly, the initial weight values can be additionally learned at a high speed by existence of the difference value memory having a small capacity.

Abstract: A reference voltage output terminal of first and second reference voltage generating circuits is connected to a first current input terminal of a current mirror circuit of an operational amplifier by a diode element. At the time of start-up, a reference voltage generated on the reference voltage output terminal is 0 V. Consequently, a current flows to the diode element and an offset voltage Voff is generated on the operational amplifier so that a malfunction point is caused to disappear. Accordingly, in the case where a normal operation point on which a reference voltage having an expected value is generated and a malfunction point on which an operation is stabilized with a reference voltage having a value less than the expected value are present, the generated reference voltage is raised at the time of start-up, passes through the malfunction point to reach an expected voltage value on the normal operation point and becomes stabilized.

Abstract: In an interpolative modulator, a signal which varies by only .+-.1 with one clock from a 1-bit quantizer is used as a shift-direction control signal. The shift-direction control signal is given to a bidirectional shift register. The bidirectional shift register shifts data based on the value of the shift-direction control signal that has been received. The output from the bidirectional shift register is given as a control signal to a resistive-ladder-type D/A converter. The resistive-ladder-type D/A converter outputs an analog potential corresponding to a switch selected by the above control signal. Therefore, if a delay difference occurs between any two bits, two adjacent switches are simply selected simultaneously, so that the output from the resistive-ladder-type D/A converter varies continuously. Consequently, there can be provided an oversampling D/A converter of resistive-ladder type with high accuracy and an increased yield, which is free from glitch (transiently generated noise).

Abstract: In a multilayered neural network for recognizing and processing characteristic data of images and the like by carrying out network arithmetical operations, characteristic data memories store the characteristic data of the layers. Coefficient memories store respective coupling coefficients of the layers other than the last layer. A weight memory stores weights of neurons of the last layer. Address converters carry out arithmetical operations to find out addresses of nets of the network whose coupling coefficients are significant. A table memory outputs a total coupling coefficient obtained by inter-multiplying the significant coupling coefficients read out from the coefficient memories of the layers. A cumulative operation unit performs cumulative additions of the product of the total coupling coefficient times the weight of the weight memory. Arithmetical operations are carried out only on particular nets with a significant coupling coefficient value. The speed of operation and recognition can be improved.

Abstract: In an information processing apparatus for implementing a neural network, if an input vector is inputted to a calculating unit, a neuron which responds to the input vector is retrieved in accordance with network interconnection information stored in a first storage unit and the neuron number indicating the retrieved neuron is written in a first register. The calculating unit reads out the internal information of the neuron stored in a second storage unit by using the neuron number, writes it in a second register, and calculates the sum of products of the outputs of the neurons and the connection loads of synapses connected to the neurons. By repeating the sequence of operations by the number of times corresponding to the total number of input vectors, a recognition process is executed. The neural network can easily be expanded by rewriting the contents of the first and second storage units.

Abstract: The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.

Abstract: In a multi-layered neural network circuit provided with an input layer having input vectors, an intermediate layer having networks in tree-like structure whose outputs are necessarily determined by the values of the input vectors and whose number corresponds to the number of the input vectors of the input layer, and an output layer having plural output units for integrating all outputs of the intermediate layer, provided are learning-time memories for memorizing the numbers of times at learning in paths between the intermediate layer and the respective output units, threshold processing circuits for threshold-processing the outputs of the leaning-time memories, and connection control circuits to be controlled by the outputs of the threshold processing circuits for controlling connection of paths between the intermediate layer and the output units. The outputs of the intermediate layer connected by the connection control circuits are summed in each output unit.

Abstract: In a direct type of finite impulse response (FIR) digital filter, direct type digital filters consisting a plurality of taps are used as a construction element of a digital filter. A pipeline structure is constructed between cascaded construction elements, and the sum and carry signals of the multi-input addition in the midst of the addition operation are transferred between cascaded construction elements. The number of gates, dissipation power, chip area and the like can be decreased as compared with a prior art inverted type digital filter. Further, a digital signal processing system such as a waveform equalizing system can be constructed using a direct type digital filter as mentioned above, and such a system includes a selector for selecting the output of the digital filter and an output in the midst of the delays in the digital filter.