Abstract: A digital signal processing system includes a plurality of multiplier/accumulators for executing a pipeline processing operation. Each of the plurality of multiplier/accumulators includes a multiplication part and an addition part. The multiplication parts includes N pipeline registers for storing N intermediate outputs of a multiplier. The addition part includes a Wallace tree transformation unit for transforming a sum of N+1 inputs into two transformation outputs, and an adder for adding the two transformation outputs. The N+1 inputs includes the N intermediate outputs from the multiplication part and the one addition output from the adder.

Abstract: A local image processor is configured as a plurality of image processor elements each having a local image memory, and a single shift register circuit for supplying to the local image memories successive local images formed of an array of pixels of a source image. Each processor element includes a register holding a count value indicating the position within the source image of data that are currently being processed by that element, and the processor elements also include mutually interconnected registers whereby intermediate computation results obtained by one processor element can be utilized by another element during parallel processing operation.

Abstract: An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.1 column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.

Abstract: An image signal processor which includes a local image register for receiving local image area data of m rows.times.n columns pixels, and a expansion use register of m row.times.l column pixels coupled to the output of the local image register. Thereby, expansion of local image area, and parallel processing can be readily conducted.