Patents by Inventor Masaki Koyama
Masaki Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8216914Abstract: An object is to provide a method for manufacturing an SOI substrate including a semiconductor film with high planarity and high crystallinity. After a single crystal semiconductor film is formed over an insulating film by a separation step, a natural oxide film existing on a surface of the semiconductor film is removed and the semiconductor film is irradiated with first laser light and second laser light under an inert gas atmosphere or a reduced-pressure atmosphere. The number of shots of the first laser light that is emitted to an arbitrary point in the semiconductor film is greater than or equal to 7, preferably greater than or equal to 10 and less than or equal to 100. The number of shots of the second laser light that is emitted to an arbitrary point in the semiconductor film is greater than 0 and less than or equal to 2.Type: GrantFiled: August 31, 2010Date of Patent: July 10, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masaki Koyama, Kosei Nei, Toru Hasegawa, Junpei Momo, Eiji Higa
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Patent number: 8172125Abstract: A vehicle door frame includes first and second door frame members which are positioned end-to-end to be butt-welded to each other, wherein each of the first and second door frame members includes a design part, an enclosed section provided on a vehicle interior side, a connecting part which connects an inner surface of the design part with the enclosed section; and first and second dam protrusions which project from the inner surface of the design part and are positioned on opposite sides of the connecting part, respectively. Molten metal is present in the first and second spaces after the molten metal has melted and passed through the inner surface of the design part from the outer surface thereof upon butted ends of the first and second door frame members being butt-welded to each other from the outer surface of the design part.Type: GrantFiled: August 30, 2010Date of Patent: May 8, 2012Assignee: Shiroki CorporationInventors: Takayuki Okada, Kenji Shimizu, Go Yamane, Masaki Koyama
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Publication number: 20120043581Abstract: In a semiconductor device, an IGBT cell includes a trench passing through a base layer of a semiconductor substrate to a drift layer of the semiconductor substrate, a gate insulating film on an inner surface of the trench, a gate electrode on the gate insulating film, a first conductivity-type emitter region in a surface portion of the base layer, and a second conductivity-type first contact region in the surface portion of the base layer. The IGBT cell further includes a first conductivity-type floating layer disposed within the base layer to separate the base layer into a first portion including the emitter region and the first contact region and a second portion adjacent to the drift layer, and an interlayer insulating film disposed to cover an end of the gate electrode. A diode cell includes a second conductivity-type second contact region in the surface portion of the base layer.Type: ApplicationFiled: August 9, 2011Publication date: February 23, 2012Inventors: Masaki KOYAMA, Yasushi Ookura, Akitaka Soeno, Tatsuji Nagaoka, Takahide Sugiyama, Sachiko Aoi, Hiroko Iguchi
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Publication number: 20120043582Abstract: There is known a semiconductor device in which an IGBT structure is provided in an IGBT area and a diode structure is provided in a diode area, the IGBT area and the diode area are both located within a same substrate, and the IGBT area is adjacent to the diode area. In this type of semiconductor device, a phenomenon that carriers accumulated within the IGBT area flow into the diode area when the IGBT structure is turned off. In order to prevent this phenomenon, a region of shortening lifetime of carriers is provided at least in a sub-area that is within said IGBT area and adjacent to said diode area. In the sub-area, emitter of IGBT structure is omitted.Type: ApplicationFiled: August 16, 2011Publication date: February 23, 2012Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masaki KOYAMA, Yasushi OOKURA, Akitaka SOENO, Tatsuji NAGAOKA, Takahide SUGIYAMA, Sachiko AOI, Hiroko IGUCHI
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Patent number: 8097901Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.Type: GrantFiled: May 25, 2011Date of Patent: January 17, 2012Assignees: Denso Corporation, Fuji Electric Device Technology Co., Ltd.Inventors: Masaki Koyama, Yoshifumi Okabe, Makoto Asai, Takeshi Fujii, Koh Yoshikawa
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Publication number: 20110308171Abstract: A vehicle door frame includes first and second door frame members which are positioned end-to-end to be butt-welded to each other, wherein each of the first and second door frame members includes a design part, an enclosed section provided on a vehicle interior side, a connecting part which connects an inner surface of the design part with the enclosed section; and first and second dam protrusions which project from the inner surface of the design part and are positioned on opposite sides of the connecting part, respectively. Molten metal is present in the first and second spaces after the molten metal has melted and passed through the inner surface of the design part from the outer surface thereof upon butted ends of the first and second door frame members being butt-welded to each other from the outer surface of the design part.Type: ApplicationFiled: August 30, 2010Publication date: December 22, 2011Applicant: SHIROKI CORPORATIONInventors: Takayuki Okada, Kenji Shimizu, Go Yamane, Masaki Koyama
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Publication number: 20110285427Abstract: A semiconductor device includes: a semiconductor substrate having a first semiconductor layer and a second semiconductor layer formed on a first surface; a diode having a first electrode and a second electrode; a control pad; a control electrode electrically coupled with the control pad; and an insulation member. The first electrode is formed on a second surface of the first semiconductor layer. The second electrode is formed on the first surface. Current flows between the first electrode and the second electrode. The control pad is arranged on the first surface so that the pad inputs a control signal for controlling an injection amount of a carrier into the first semiconductor layer. The insulation member insulates between the control electrode and the second electrode and between the control electrode and the semiconductor substrate.Type: ApplicationFiled: May 17, 2010Publication date: November 24, 2011Applicant: DENSO CORPORATIONInventors: Masaki Koyama, Yutaka Fukuda
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Patent number: 8048773Abstract: A single crystal semiconductor separated from a single crystal semiconductor substrate is formed partly over a supporting substrate with a buffer layer provided therebetween. The single crystal semiconductor is separated from the single crystal semiconductor substrate by irradiation with accelerated ions, formation of a fragile layer by the ion irradiation, and heat treatment. A non-single crystal semiconductor layer is formed over the single crystal semiconductor and irradiated with a laser beam to be crystallized, whereby an SOI substrate is manufactured.Type: GrantFiled: March 23, 2010Date of Patent: November 1, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masaki Koyama, Kosei Noda, Kenichiro Makino, Hideto Ohnuma, Kosei Nei
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Patent number: 8030177Abstract: An object is to provide a method for manufacturing an SOI substrate including a single crystal silicon film whose plane orientation is (100) and a single crystal silicon film whose plane orientation is (110) with high yield. A first single crystal silicon substrate whose plane orientation is (100) is doped with first ions to form a first embrittlement layer. A second single crystal silicon substrate whose plane orientation is (110) is doped with second ions to selectively form a second embrittlement layer. Only part of the first single crystal silicon substrate is separated along the first embrittlement layer by first heat treatment, thereby forming a first single crystal silicon film. A region of the second single crystal silicon substrate, in which the second embrittlement layer is not formed, is removed. Part of the second single crystal silicon substrate is separated along the second embrittlement layer by second heat treatment, thereby forming a second single crystal silicon film.Type: GrantFiled: November 10, 2009Date of Patent: October 4, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Masaki Koyama, Yasuhiro Jinbo, Naoki Okuno
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Publication number: 20110220962Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.Type: ApplicationFiled: May 25, 2011Publication date: September 15, 2011Applicants: DENSO CORPORATION, Fuji Electric Device Technology Co., Ltd.Inventors: Masaki Koyama, Yoshifumi Okabe, Makoto Asai, Takeshi Fujii, Koh Yoshikawa
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Patent number: 7977704Abstract: A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer.Type: GrantFiled: January 27, 2009Date of Patent: July 12, 2011Assignees: Denso Corporation, Fuji Electric Device Technology Co., Ltd.Inventors: Masaki Koyama, Yoshifumi Okabe, Makoto Asai, Takeshi Fujii, Koh Yoshikawa
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Publication number: 20110115046Abstract: Methods for manufacturing a semiconductor substrate and a semiconductor device by which a high-performance semiconductor element can be formed are provided. A single crystal semiconductor substrate including an embrittlement layer and a base substrate are bonded to each other with an insulating layer interposed therebetween, and the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment to fix a single crystal semiconductor layer over the base substrate. Next, a plurality of regions of a monitor substrate are irradiated with laser light under conditions of different energy densities, and carbon concentration distribution and hydrogen concentration distribution in a depth direction of each region of the single crystal semiconductor layer which has been irradiated with the laser light is measured.Type: ApplicationFiled: January 21, 2011Publication date: May 19, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Akihisa SHIMOMURA, Masaki KOYAMA, Motoki NAKASHIMA
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Patent number: 7932164Abstract: Methods for manufacturing a semiconductor substrate and a semiconductor device by which a high-performance semiconductor element can be formed are provided. A single crystal semiconductor substrate including an embrittlement layer and a base substrate are bonded to each other with an insulating layer interposed therebetween, and the single crystal semiconductor substrate is separated along the embrittlement layer by heat treatment to fix a single crystal semiconductor layer over the base substrate. Next, a plurality of regions of a monitor substrate are irradiated with laser light under conditions of different energy densities, and carbon concentration distribution and hydrogen concentration distribution in a depth direction of each region of the single crystal semiconductor layer which has been irradiated with the laser light is measured.Type: GrantFiled: March 12, 2009Date of Patent: April 26, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Masaki Koyama, Motoki Nakashima
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Publication number: 20110092050Abstract: A first embrittlement layer is formed by doping a first single-crystal semiconductor substrate with a first ion; a second embrittlement layer is formed by doping a second single-crystal semiconductor substrate with a second ion; the first and second single-crystal semiconductor substrates are bonded to each other; the first single-crystal semiconductor film is formed over the second single-crystal semiconductor substrate by a first heat treatment; an insulating substrate is bonded over the first single-crystal semiconductor film; and the first and second single-crystal semiconductor films are formed over the insulating substrate by a second heat treatment. A dose of the first ion is higher than that of the second ion and a temperature of the first heat treatment is lower than that of the second heat treatment.Type: ApplicationFiled: October 8, 2010Publication date: April 21, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Akihisa SHIMOMURA, Naoki OKUNO, Masaki KOYAMA, Yasuhiro JINBO
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Patent number: 7920611Abstract: It is an object to provide a laser apparatus, a laser irradiating method and a manufacturing method of a semiconductor device that make laser energy more stable. To attain the object, a part of laser beam emitted from an oscillator is sampled to generate an electric signal that contains as data energy fluctuation of a laser beam. The electric signal is subjected to signal processing to calculate the frequency, amplitude, and phase of the energy fluctuation of the laser beam.Type: GrantFiled: December 18, 2007Date of Patent: April 5, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tamae Takano, Masaki Koyama, Koichiro Tanaka
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Publication number: 20110053384Abstract: An object is to provide a method for manufacturing an SOI substrate including a semiconductor film with high planarity and high crystallinity. After a single crystal semiconductor film is formed over an insulating film by a separation step, a natural oxide film existing on a surface of the semiconductor film is removed and the semiconductor film is irradiated with first laser light and second laser light under an inert gas atmosphere or a reduced-pressure atmosphere. The number of shots of the first laser light that is emitted to an arbitrary point in the semiconductor film is greater than or equal to 7, preferably greater than or equal to 10 and less than or equal to 100. The number of shots of the second laser light that is emitted to an arbitrary point in the semiconductor film is greater than 0 and less than or equal to 2.Type: ApplicationFiled: August 31, 2010Publication date: March 3, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Masaki KOYAMA, Kosei NEI, Toru HASEGAWA, Junpei MOMO, Eiji HIGA
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Publication number: 20110053347Abstract: It is an object to provide a method for manufacturing an SOI substrate in which reduction in yield can be suppressed while impurity diffusion into a semiconductor film is suppressed. A semiconductor substrate provided with an oxide film is formed by thermally oxidizing the surface of the semiconductor substrate. Plasma is generated under an atmosphere of a gas containing nitrogen atoms and plasma nitridation is performed on part of the oxide film, so that a semiconductor substrate in which an insulating film containing nitrogen atoms is formed over the oxide film is obtained. After bonding the insulating film containing nitrogen atoms and a glass substrate to each other, the semiconductor substrate is split, whereby an SOI substrate in which the insulating film containing nitrogen atoms, the oxide film, a thin semiconductor film are stacked in this order is formed.Type: ApplicationFiled: August 31, 2010Publication date: March 3, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Akihisa SHIMOMURA, Masaki KOYAMA, Toru HASEGAWA
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METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE MANUFACTURING APPARATUS
Publication number: 20110030901Abstract: An object is to provide a uniform semiconductor substrate in which defective bonding is reduced. A further object is to manufacture the semiconductor substrate with a high yield. A first substrate and a second substrate are bonded in a reduced-pressure atmosphere by placing the first substrate at a certain region surrounded by an airtight holding mechanism provided over a support to surround the certain region of a surface of the support; placing the second substrate so as to come to be in contact with the airtight holding mechanism to ensure airtightness of a space surrounded by the support, the airtight holding mechanism, and the second substrate; evacuating the space whose airtightness is secured, thereby reducing an pressure in the space; disposing the second substrate in close contact with the first substrate using difference between the pressure in the space and outside atmospheric pressure; and performing heat treatment.Type: ApplicationFiled: October 13, 2010Publication date: February 10, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Akihisa SHIMOMURA, Masaki KOYAMA, Satohiro OKAMOTO -
Patent number: 7881350Abstract: It is an object to provide a laser apparatus, a laser irradiating method and a manufacturing method of a semiconductor device that can perform uniform a process with a laser beam to an object uniformly. The present invention provides a laser apparatus comprising an optical system for sampling a part of a laser beam emitted from an oscillator, a sensor for generating an electric signal including fluctuation in energy of the laser beam as a data from the part of the laser beam, a means for performing signal processing to the electrical signal to grasp a state of the fluctuation in energy of the laser beam, and controlling a relative speed of an beam spot of the laser beam to an object in order to change in phase with the fluctuation in energy of the laser beam.Type: GrantFiled: April 5, 2007Date of Patent: February 1, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tamae Takano, Masaki Koyama
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Publication number: 20110012195Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).Type: ApplicationFiled: January 28, 2009Publication date: January 20, 2011Applicants: FUJI ELECTRIC SYSTEMS CO., LTD., DENSO CORPORATIONInventors: Seiji Momota, Hitoshi Abe, Takashi Shiigi, Takeshi Fujii, Koh Yoshikawa, Tetsutaro Imagawa, Masaki Koyama, Makoto Asai