Patents by Inventor Masaki Tsukude
Masaki Tsukude has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7145832Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: GrantFiled: May 8, 2006Date of Patent: December 5, 2006Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Publication number: 20060209611Abstract: In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.Type: ApplicationFiled: March 15, 2006Publication date: September 21, 2006Inventor: Masaki Tsukude
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Patent number: 7111112Abstract: In a freeze reset circuit in a semiconductor memory device, when a row act signal is not activated in a predetermined period determined by a trailing edge delay circuit after a chip enable signal is set to the H level during a write or read operation, a freeze reset signal is output from a logic gate after a predetermined period. As a result, the semiconductor memory device terminates the write or read operation. Therefore, the semiconductor memory device can ensure the stability of the write or read operation.Type: GrantFiled: October 15, 2002Date of Patent: September 19, 2006Assignee: Renesas Technology Corp.Inventor: Masaki Tsukude
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Publication number: 20060203607Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: ApplicationFiled: May 8, 2006Publication date: September 14, 2006Applicant: RENESAS TECHNOLOGY CORP.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Patent number: 7061828Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: GrantFiled: September 1, 2005Date of Patent: June 13, 2006Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Publication number: 20060050587Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: ApplicationFiled: September 1, 2005Publication date: March 9, 2006Applicant: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Patent number: 6956758Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: GrantFiled: February 3, 2005Date of Patent: October 18, 2005Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Publication number: 20050169091Abstract: A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.Type: ApplicationFiled: February 3, 2005Publication date: August 4, 2005Applicant: Renesas Technology Corp.Inventors: Takeo Miki, Seiji Sawada, Masaki Tsukude
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Publication number: 20050141337Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: ApplicationFiled: February 3, 2005Publication date: June 30, 2005Applicant: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Patent number: 6891770Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.Type: GrantFiled: August 18, 2004Date of Patent: May 10, 2005Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Patent number: 6882586Abstract: A semiconductor memory device is provided with a memory cell array including memory cells being arranged in a shape of matrix and requiring a refresh operation. In the semiconductor memory device, a control circuit controls a timing of the refresh operation in accordance with an internal signal independently of an external signal and controlling the memory cell array in a non-normal operation mode different from a normal operation mode for writing data into the memory cell array and reading out data from the memory cell array. The control circuit starts the non-normal operation mode in response to a sequence of entry into the non-normal operation mode based on a predetermined first command signal, sets the non-normal operation mode in response to a sequence of setting the non-normal operation mode based on a predetermined second command signal, and thereafter, executes operation of the corresponding non-normal operation mode which is set.Type: GrantFiled: October 10, 2002Date of Patent: April 19, 2005Assignee: Renesas Technology Corp.Inventors: Hirotoshi Sato, Masaki Tsukude
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Patent number: 6859403Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss?, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss?.Type: GrantFiled: April 2, 2004Date of Patent: February 22, 2005Assignee: Renesas Technology Corp.Inventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Patent number: 6859415Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.Type: GrantFiled: January 28, 2003Date of Patent: February 22, 2005Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Publication number: 20050018529Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.Type: ApplicationFiled: August 18, 2004Publication date: January 27, 2005Applicant: RENESAS TECHNOLOGY CORP.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Patent number: 6813211Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.Type: GrantFiled: January 15, 2003Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventors: Takafumi Takatsuka, Hirotoshi Sato, Masaki Tsukude
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Patent number: 6798236Abstract: A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the first circuit.Type: GrantFiled: October 17, 2002Date of Patent: September 28, 2004Assignee: Renesas Technology Corp.Inventors: Tadayuki Shimizu, Takafumi Takatsuka, Masaki Tsukude
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Publication number: 20040184332Abstract: Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss′, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss′.Type: ApplicationFiled: April 2, 2004Publication date: September 23, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hideto Hidaka, Mikio Asakura, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima, Masaki Tsukude
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Patent number: 6795943Abstract: A semiconductor memory includes a first decoder selecting any of modes 1-n of a test mode B according to first to fourth data signals, and a second decoder selecting any of modes 1-n of the test mode B according to fifth to eighth data signals. When a predetermined mode m+1 is not set in a test mode A, the mode selected by both the first and second decoders is set. When the predetermined mode m+1 is set, the mode selected by the first decoder is set. Therefore, the test mode B can be set at the manufacturer side by connecting only four data input/output terminals to the tester.Type: GrantFiled: October 11, 2001Date of Patent: September 21, 2004Assignee: Renesas Technology Corp.Inventors: Hirotoshi Sato, Masaki Tsukude, Ryu Makabe
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Patent number: 6744679Abstract: A DRAM performs data writing if a column activation signal ZCOLRE is activated with changing of an internal address Add and then an internal write control signal WDRV is activated by generation of a write signal WE from an outside. However, in order to solve a problem that data writing does not performed in some cases when the data writing is performed at optional timing, a semiconductor memory device according to the present invention includes a delay unit, thereby delaying an output of the internal write control signal WDRV until the column activation signal ZCOLRE is activated, even when the write signal WE is generated.Type: GrantFiled: September 16, 2002Date of Patent: June 1, 2004Assignee: Renesas Technology Corp.Inventors: Hirotoshi Sato, Masaki Tsukude, Takafumi Takatsuka
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Patent number: 6737906Abstract: In operation, a charge pumping circuit supplies negative charges to an internal voltage line so as to reduce a negative internal voltage. A voltage dividing circuit produces a control voltage according to the difference between a first positive voltage externally applied to a first input terminal in the test mode and the internal voltage. A comparison circuit operates the charge pumping circuit according to the comparison result between a second positive voltage externally applied to a second input terminal in the test mode and the control voltage. The second positive voltage is set according to a target value of the negative internal voltage.Type: GrantFiled: November 13, 2001Date of Patent: May 18, 2004Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Masaki Tsukude