Patents by Inventor Masaki Utsumi
Masaki Utsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9673154Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: May 5, 2016Date of Patent: June 6, 2017Assignee: PANASONIC CORPORATIONInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20160247771Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: May 5, 2016Publication date: August 25, 2016Inventors: Makoto TSUTSUE, Masaki UTSUMI
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Patent number: 9082779Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: March 31, 2014Date of Patent: July 14, 2015Assignee: PANASONIC CORPORATIONInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20150194391Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: March 19, 2015Publication date: July 9, 2015Inventors: Makoto TSUTSUE, Masaki UTSUMI
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Publication number: 20140210056Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: Panasonic CorporationInventors: Makoto TSUTSUE, Masaki UTSUMI
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Patent number: 8710595Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: July 12, 2013Date of Patent: April 29, 2014Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Patent number: 8618618Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: July 17, 2012Date of Patent: December 31, 2013Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20130299948Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: July 12, 2013Publication date: November 14, 2013Inventors: Makoto TSUTSUE, Masaki UTSUMI
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Patent number: 8508002Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: July 17, 2012Date of Patent: August 13, 2013Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20120280401Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: July 17, 2012Publication date: November 8, 2012Applicant: Panasonic CorporationInventors: Makoto TSUTSUE, Masaki UTSUMI
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Patent number: 8247876Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: June 28, 2011Date of Patent: August 21, 2012Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20120018820Abstract: A semiconductor device includes a converter that converts an acoustic pressure into an electrical signal and an amplifier element that includes an amplifier circuit that amplifies the electrical signal outputted from the converter. The converter includes a pedestal including a cavity formed from an upper face to a lower face thereof, and a vibration film located so as to cover an opening of the cavity on the side of the upper face. The vibration film vibrates in accordance with the acoustic pressure to thereby convert the acoustic pressure into an electrical signal. The amplifier element is located under the converter so as to cover the cavity.Type: ApplicationFiled: September 28, 2011Publication date: January 26, 2012Applicant: PANASONIC CORPORATIONInventors: Masaki UTSUMI, Kyoko FUJII, Takahiro NAKANO
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Publication number: 20110254136Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: ApplicationFiled: June 28, 2011Publication date: October 20, 2011Applicant: Panaconic CorporationInventors: Makoto TSUTSUE, Masaki Utsumi
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Publication number: 20110204487Abstract: A semiconductor device includes: a semiconductor substrate; a through electrode passing through the semiconductor substrate in a thickness direction of the semiconductor substrate; an internal electrode provided in a part of the top surface of the semiconductor substrate and electrically connected to the through electrode which reaches the part; a first protective film covering the top surface except a part of the internal electrode; a second protective film formed apart from the first protective film, on the part of the internal electrode, the part being not covered by the first protective film; and metal wiring formed on the back surface of the semiconductor substrate and electrically connected to the through electrode, the second main surface being on a side of the semiconductor substrate opposite the first main surface.Type: ApplicationFiled: May 4, 2011Publication date: August 25, 2011Applicant: PANASONIC CORPORATIONInventors: TAKAHIRO NAKANO, MASAKI UTSUMI, HIKARI SANO
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Patent number: 7994589Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: August 18, 2010Date of Patent: August 9, 2011Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20110147905Abstract: In a semiconductor element, upper through-hole conductor portions and lower through-hole conductor portions are formed such that pore size A of the joint surface of the upper through-hole conductor portion and the lower through-hole conductor portion is smaller than pore size B of the upper through-hole conductor portion on the major surface of the semiconductor element and pore size C of the lower through-hole conductor portion on the other surface of the semiconductor element. Further, electrode portions are formed respectively on the top surfaces of the upper through-hole conductor portions and protrusions 4 are formed respectively on the top surfaces of the electrode portions. Moreover, an optical member pressed in contact with the protrusions is fixed on the semiconductor element with an adhesive.Type: ApplicationFiled: March 3, 2011Publication date: June 23, 2011Applicant: PANASONIC CORPORATIONInventors: Masaki Utsumi, Hikari Sano, Hiroaki Fujimoto, Yoshihiro Tomita
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Publication number: 20110147871Abstract: To provide a semiconductor device and a method of manufacturing the same, which have a device structure ensuring high degrees of reliability and mass-productivity at low cost. A semiconductor device includes: a substrate including an imaging area and having a first main surface and a second main surface; an electrode formed on the first main surface; an external electrode formed on the second main surface; a conductive portion which is formed in a through hole penetrating the substrate, and electrically connects the electrode and the external electrode; an optical element which is placed on the first main surface and has a convex surface including a convex portion; and a light transmitting element which is bonded to the optical element so as to cover the convex portion and has a flat upper surface.Type: ApplicationFiled: February 28, 2011Publication date: June 23, 2011Applicant: PANASONIC CORPORATIONInventors: Masaki UTSUMI, Takahiro NAKANO, Hikari SANO
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Patent number: 7948039Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.Type: GrantFiled: November 4, 2008Date of Patent: May 24, 2011Assignee: Panasonic CorporationInventors: Makoto Tsutsue, Masaki Utsumi
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Publication number: 20110108957Abstract: A semiconductor substrate (1) includes a plurality of semiconductor elements (2) in which functional elements are constructed and which is formed in a grid pattern, wherein continuous linear grooves (3) are formed on longitudinal and lateral separating lines (4) that individually separate the plurality of semiconductor elements (2) with the exception of intersections of the separating lines (4) and portions corresponding to corners of each semiconductor element (2).Type: ApplicationFiled: December 8, 2010Publication date: May 12, 2011Applicant: Panasonic CorporationInventors: Masaki Utsumi, Takahiro Kumakawa
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Publication number: 20110039365Abstract: A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film.Type: ApplicationFiled: October 27, 2010Publication date: February 17, 2011Applicant: PANASONIC CORPORATIONInventors: Masaki UTSUMI, Takahiro Kumakawa, Masami Matsuura, Yoshihiro Matsushima