Abstract: A semiconductor substrate (1) includes a plurality of semiconductor elements (2) in which functional elements are constructed and which is formed in a grid pattern, wherein continuous linear grooves (3) are formed on longitudinal and lateral separating lines (4) that individually separate the plurality of semiconductor elements (2) with the exception of intersections of the separating lines (4) and portions corresponding to corners of each semiconductor element (2).

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Abstract: A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film.

Abstract: Vias 7 penetrating a circuit substrate 2 or a seal ring 8 are provided on a part or the entire outer periphery of a molding semiconductor device 1 or in the cut region of the circuit substrate 2, so that adhesion between a substrate and a core 2C in the circuit substrate 2 is improved. Therefore, it is possible to suppress the exfoliation of the circuit substrate 2, improving the yields.

Abstract: A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film.

Abstract: A semiconductor substrate (1) includes a plurality of semiconductor elements (2) in which functional elements are constructed and which is formed in a grid pattern, wherein continuous linear grooves (3) are formed on longitudinal and lateral separating lines (4) that individually separate the plurality of semiconductor elements (2) with the exception of intersections of the separating lines (4) and portions corresponding to corners of each semiconductor element (2).

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Abstract: Vias 7 penetrating a circuit substrate 2 or a seal ring 8 are provided on a part or the entire outer periphery of a molding semiconductor device 1 or in the cut region of the circuit substrate 2, so that adhesion between a substrate and a core 2C in the circuit substrate 2 is improved. Therefore, it is possible to suppress the exfoliation of the circuit substrate 2, improving the yields.

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Abstract: A plurality of semiconductor elements and division regions are provided on a semiconductor subsubstrate. A modification region is provided in the semiconductor substrate. A division guide pattern is provided at least in a portion of each division region. A cleavage produced from a starting point corresponding to the modification region is guided by the division guide pattern.

Abstract: A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer 101 to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film.

Abstract: A plurality of semiconductor elements and division regions are provided on a semiconductor substrate. A modification region is provided in the semiconductor substrate. A division guide pattern is provided at least in a portion of each division region. A cleavage produced from a starting point corresponding to the modification region is guided by the division guide pattern.

Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.

Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.

Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.

Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.

Abstract: The server computer 155 is provided with an access section 151, a security section 152, a application function conversion section 153, application service supply section 154 and a remote agent 155 therein. The data terminals 13 is provided with a local agent 131, client software 132, key management client 133, enciphering section 134 therein. In this way, the server computer 15 and the data terminals 13 connected through a network 14 can realize a countermeasure for the circuit breakdown and an improvement of the security function regarding the data cache function and vicarious login.

Abstract: A lead frame includes: an outer frame section; a plurality of chip mounting sections which are supported by the outer frame section and on which a plurality of semiconductor chips are mounted; lead sections surrounding the chip mounting sections; connecting sections for connecting and supporting the lead sections and the outer frame section with each other; and an encapsulation region in which the chip mounting sections are encapsulated together in an encapsulation resin. An opening is provided in a plurality of regions of the outer frame section that are each located outside the encapsulation region and along the extension of one of the connecting sections.

Abstract: The server computer 155 is provided with an access section 151, a security section 152, a application function conversion section 153, application service supply section 154 and a remote agent 155 therein. The data terminals 13 is provided with a local agent 131, client software 132, key management client 133, enciphering section 134 therein. In this way, the server computer 15 and the data terminals 13 connected through a network 14 can realize a countermeasure for the circuit breakdown and an improvement of the security function regarding the data cache function and vicarious login.

Abstract: A data exchange unit is arranged in a server. Service data provided as an application service is converted into a predetermined format on the basis of the attribute data of a terminal as a communication partner and is transmitted. With this processing, the application service can be provided while adjusting the relative difference in processing capability terminals. When the service data is converted into a predetermined format on the basis of the attribute of a communication network connected to the terminal and transmitted, the application service can be provided while adjusting the relative difference in communication capability among communication networks. Also, terminal equipment 51 is able to communicate with server computer while keeping the security function.