Patents by Inventor Masanori Kasai

Masanori Kasai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060203123
    Abstract: Vertical signal lines are connected to each pixel column in an image pickup unit having pixels arranged in arrays, and the vertical signal lines are connected to a voltage supply circuit for supplying a voltage between a power source voltage and a reference voltage.
    Type: Application
    Filed: March 9, 2006
    Publication date: September 14, 2006
    Inventor: Masanori Kasai
  • Publication number: 20060132642
    Abstract: Noises are reduced in an image picked up in natural light without using lighting equipment that affect the picked up image. The present invention provides an image processing apparatus that includes an image acquisition unit that acquires a visible light image and an invisible light image corresponding to the visible light image, and a noise reduction unit that reduces noises of the visible light image by using the invisible light image.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 22, 2006
    Inventors: Hajime Hosaka, Masanori Kasai
  • Patent number: 6899756
    Abstract: A drier for oxidative polymerization-drying printing ink is provided, which does not contain cobalt capable of exerting an adverse influence on the environment and health and which is environmentally friendly. A printing ink containing the drier is also provided. The drier for oxidative polymerization-drying printing ink contains a cerium salt of a fatty acid and a manganese salt of a fatty acid.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: May 31, 2005
    Assignee: Dainippon Ink and Chemicals, Inc.
    Inventors: Makoto Nomura, Kosaku Nishiyama, Masanori Kasai, Hideo Ishii
  • Publication number: 20050001915
    Abstract: A CMOS sensor has unit pixels each structured by a light receiving element and three transistors, to prevent against the phenomenon of saturation shading and the reduction of dynamic range. The transition time (fall time), in switching off the voltage on a drain line shared in all pixels, is given longer than the transition time in turning of any of the reset line and the transfer line. For this reason, the transistor constituting a DRN drive buffer is made proper in its W/L ratio. Meanwhile, a control resistance or current source is inserted on a line to the GND, to make proper the operation current during driving. This reduces saturation shading amount. By making a reset transistor in a depression type, the leak current to a floating diffusion is suppressed to broaden the dynamic range.
    Type: Application
    Filed: April 16, 2004
    Publication date: January 6, 2005
    Inventors: Keiji Mabuchi, Eiichi Funatsu, Masanori Kasai
  • Publication number: 20040040468
    Abstract: A drier for oxidative polymerization-drying printing ink is provided, which does not contain cobalt capable of exerting an adverse influence on the environment and health and which is environmentally friendly. A printing ink containing the drier is also provided. The drier for oxidative polymerization-drying printing ink contains a cerium salt of a fatty acid and a manganese salt of a fatty acid.
    Type: Application
    Filed: March 11, 2003
    Publication date: March 4, 2004
    Applicant: DAINIPPON INK AND CHEMICALS, INC.
    Inventors: Makoto Nomura, Kosaku Nishiyama, Masanori Kasai, Hideo Ishii
  • Patent number: 6680861
    Abstract: A ferroelectric memory comprises a first memory cell which is provided at a point where a first word line and a first or second bit line intersect, and has a first ferroelectric capacitor formed with a ferroelectric material as an insulating film, capacitor; a first sense amplifier connected to the first and second bit lines, for amplifying a signal read from the first memory cell; a second memory cell which is provided at a point where a second word line and a third or fourth bit line intersect, and has a second ferroelectric capacitor formed with a ferroelectric material as an insulating film; a second sense amplifier connected to the third and fourth bit lines, for amplifying a signal read from the second memory cell; a first switch for electrically connecting the first bit line and the third bit line; and a second switch for electrically connecting the second bit line and the fourth bit line.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: January 20, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Masanori Kasai
  • Patent number: 6600674
    Abstract: Bit lines to which memory cells having a capacitor formed of a ferroelectric substance are connected are each divided into a plurality of line segments. These line segments can be electrically connected by transistors. To read data from the memory cells to the bit lines, the transistors are rendered conductive, and the parasitic capacitances of the bit lines are increased. To amplify data on a bit line using a sense amplifier, the transistors are rendered off and the parasitic capacitances of the bit lines are reduced.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: July 29, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Masanori Kasai
  • Publication number: 20030063488
    Abstract: A ferroelectric memory comprises a first memory cell which is provided at a point where a first word line and a first or second bit line intersect, and has a first ferroelectric capacitor formed with a ferroelectric material as an insulating film, and a first transistor having a control electrode connected to the first word line, a first electrode connected to the first or second bit line, and a second electrode connected to a first electrode of the first ferroelectric capacitor; a first sense amplifier connected to the first and second bit lines, for amplifying a signal read from the first memory cell; a second memory cell which is provided at a point where a second word line and a third or fourth bit line intersect, and has a second ferroelectric capacitor formed with a ferroelectric material as an insulating film, and a second transistor having a control electrode connected to the second word line, a first electrode connected to the third or fourth bit line, and a second electrode connected to a first elec
    Type: Application
    Filed: July 12, 2002
    Publication date: April 3, 2003
    Inventor: Masanori Kasai
  • Publication number: 20020101756
    Abstract: Bit lines to which memory cells having a capacitor formed of a ferroelectric substance are connected are each divided into a plurality of line segments. These line segments can be electrically connected by transistors. To read data from the memory cells to the bit lines, the transistors are rendered conductive, and the parasitic capacitances of the bit lines are increased. To amplify data on a bit line using a sense amplifier, the transistors are rendered off and the parasitic capacitances of the bit lines are reduced.
    Type: Application
    Filed: January 28, 2002
    Publication date: August 1, 2002
    Inventor: Masanori Kasai
  • Patent number: 6269019
    Abstract: Bit line capacitance variation devices are respectively connected to the bit lines contained in a ferroelectric memory device. These bit line capacitance variation devices change the capacitance of bit lines according to the bit line potential during operations for reading data from the ferroelectric memory device.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: July 31, 2001
    Assignee: Oki Electric Industry, Co., Ltd.
    Inventor: Masanori Kasai
  • Patent number: 4838331
    Abstract: In a shutter equipment having a shutter for opening and closing an opening portion such as a building entrance, window or the like the shutter being composed of plural slats positioned in a vertically adjacent relation when the shutter is closed, the slats being wound up and pulled down continuously to stow the slats and close the opening portion, respectively; a slat opening/closing mechanism substantially composed of vertical guide rails disposed vertically on both sides of the opening portion; a box positioned on top of the vertical guide rails to stow the slats transversely in parallel in a vertically suspended state; a pair of right and left endless chains which are movable from the vertical guide rails into the slat stowing box and to which are secured through shafts both end faces of the upper portion of each slat; a vertical slat drive mechanism for winding up and pulling down the chains to raise and lower the slats in a suspended state from the vertical guide rails toward the upper portion of the box
    Type: Grant
    Filed: September 30, 1987
    Date of Patent: June 13, 1989
    Assignees: Bunka Shutter Co., Ltd., Lumitter Industry Co., Ltd.
    Inventor: Masanori Kasai