Abstract: A booster circuit including a precharge capacitor (C.sub.2), a precharge driver circuit (20) having a first bootstrap circuit (C.sub.59, Q.sub.58, Q.sub.61) and precharging a voltage to the precharge capacitor in a reset mode, and an output driver circuit (19) having a switching circuit (Q.sub.21) for cutting off the output of the precharged voltage of the precharged capacitor in the reset mode and a second bootstrap circuit driving the switching circuit in an operation mode. The booster circuit further includes an additional switching circuit (Q.sub.1) for outputting a voltage to be superimposed onto the precharge voltage in the operation mode.The booster circuit may be applicable to a dynamic semiconductor memory device, for boosting a voltage of a word line at a high speed and for improving integration.

Abstract: A circuit for storing information by blown and unblown fuses has at least two fuses per bit and an information output circuit. The information output circuit discriminates between the state in which all the fuses are unblown and the state in which at least one of the fuses is blown, and provides an output in accordance with the result of the discrimination as stored information.

Abstract: A semiconductor integrated circuit which includes therein at least one inspection circuit for inspecting a voltage level produced at an internal node to be inspected. The inspection circuit has at least a control signal input portion connected to the internal node to be inspected and an input part connected to an external input/output pin. The inspection circuit includes a series-connected transistor and diode connected between a power source and the input portion, a capacitor connected between a gate of the transistor and the input portion, and a transfer gate transistor connected between the control signal input portion and the gate of the transistor. The inspection circuit discriminates the level at the internal node according to a flow or nonflow of a current, via the external input/output pin, when a particular signal having a voltage level higher than the power source level is supplied to the external input/output pin.

Abstract: An MIS transistor circuit which is operated alternately in a reset state and in an active state, comprises a voltage holding circuit for holding a power supply voltage applied in each reset state so as to provide a clamped voltage. The clamped voltage is applied during each active state to the desired nodes of the MIS transistor circuit as an actual power supply voltage, whereby error operation due to voltage fluctuation of the power supply voltage is prevented.

Abstract: A dynamic semiconductor memory device of an open bit-line type includes a plurality of first wiring lines running on common opposite electrodes for forming opposite electrodes of memory cell capacitors and connected to the common opposite electrodes at a number of contact points. A second wiring line is connected to the ends of the first wiring lines and to a voltage supply line at the center point of the second wiring line, so that the potential distribution of the common opposite electrodes can be equalized precisely.

Abstract: A semiconductor device comprising a substrate voltage-generating circuit which has an oscillating circuit and a pumping circuit. The substrate voltage-generating circuit also has a control circuit for controlling the application of the output signal of the oscillating circuit to the pumping circuit and a terminal electrode for receiving an external signal to control the control circuit and to stop the application of the output signal of the oscillating circuit to the pumping circuit.

Abstract: A dynamic random access memory device which comprises one-transistor, one-capacitor-type memory cells (C.sub.00 .about.C.sub.127,127) in rows and columns and dummy cells (DC.sub.20 '.about.DC.sub.2,127 ', DC.sub.20 ".about.DC.sub.2,127 ", DC.sub.20 "'.about.DC.sub.2,127 "') in rows. The capacitors (C.sub.d) of the dummy cells are charged to a high power supply potential (V.sub.CC) by one or more charging transistors (Q.sub.A or Q.sub.A ') clocked by a reset clock signal (.phi..sub.R). The capacitors (C.sub.d) of the dummy cells are discharged to a low power supply potential (V.sub.SS) by one or more transistors (Q.sub.B or Q.sub.B ') clocked by an operation clock signal (.phi..sub.WL) having a potential lower than the high power supply potential (V.sub.CC).

Abstract: A speaker driving circuit for use with an audio amplifier made selectively ineffective comprising switching means for providing intermittent current to the speaker when said means is energized.

Abstract: A bias-voltage generator suitable for measuring a substrate leakage current is disclosed. The bias-voltage generator comprises of an oscillator, a charge-pumping circuit which is driven by the oscillator via a pumping capacitor, and a charge-pumping switch. The charge-pumping switch is connected in series with the charge-pumping circuit. The charge-pumping switch cooperates with an external electrode for controlling the ON or OFF condition of the charge pumping circuit. The charge-pumping switch is turned OFF by the external electrode becoming a floating state and a resistor employed to ensure the charge pumping switch is inoperable after the above-mentioned measurement is completed and the circuit is shipped from the factory.

Abstract: A DC motor control apparatus is disclosed comprising a first pair of switching elements coupled respectively with oppositely poled ends of the DC motor. A first actuating means is provided for actuating one of a first pair of switching elements in response to an input signal of a first predetermined logic content. The other of the first pair of switching elements is provided to respond to an input signal of a second predetermined logic content. Also provided, are means for applying a driving potential to the oppositely poled end of a motor simultaneously with the actuation of each of the first pair of switching elements, thereby establishing a current path for forward direction and reverse direction operation of said DC motor, respectively. A second pair of switching elements are respectively connected to oppositely poled ends of the DC motor.

Abstract: A semiconductor memory device has fuses coated with a protecting layer. The protecting layer is selectively etched to open windows so as to expose narrow center portions of the fuses. After the opening of the center windows, the fusing operation of the fuses is carried out to open a gap in the center window portion of the fuse material. In a preferred embodiment, another protective layer is then added to fill the gaps in the blown fuses.

Abstract: A semiconductor integrated circuit device includes a circuit for supplying a reference voltage which is generated in a reference voltage generator circuit to plural load circuits. A plurality of noise limiters have one end commonly connected to the output of the reference voltage generator and another end respectively connected to a corresponding load circuit. The value of the impedance of the noise limiters is of the same order or larger than the output impedance of the reference voltage generator circuit, and capacitors for eliminating the noise may be provided between each noise limiter and each load circuit.

Abstract: An automatic back-up circuitry for use with a memory circuit or the like including a switch transistor adapted to turn on in response to the application of an operative current and conduct it to the memory circuit, said transistor being also adapted to turn off when the application of the main operative current to said transistor is release, whereupon the back-up voltage is applied to the path between the transistor and the memory circuit.

Abstract: A semiconductor memory device wherein a redundancy memory cell array incorporated with main memory cell matrixes is disclosed. Memory cells of the main memory cell matrixes are selected by first and third decoders while memory cells of the redundancy memory cell array are selected by second and third decoders. When the redundancy memory cell array is selected by the second decoder, the transmission of a clock signal to the first decoders is stopped by a switching circuit.

Abstract: A boosting circuit boosts a voltage of a load capacitor which is charged by a specific voltage. The boosting circuit comprises a boosting capacitor one end of which is connected to receive a clock signal, a charging circuit for charging the boosting capacitor, a gate circuit provided between the load capacitor and the other end of the boosting capacitor, and a gate control circuit for opening the gate circuit upon discharging of the charge of the boosting, that is controlled by the clock signal, to the load capacitor and for closing the gate circuit during discharging of the load capacitor. The charging circuit is provided separately from a circuit for supplying the specific voltage. The charges of the boosting capacitor under the control of the clock signal flow through the gate circuit to the load capacitor.

Abstract: A blade of the fan wheel of a diagonal-flow fan, which blade should ideally have a shape of a twisted double-curvature or undevelopable surface, is formed from a portion of a cylinder, which has a single-curvature or developable surface. To realize the formation of a blade from the single-curvature surface, lines of intersection between a cylinder and a number of coaxial imaginary conical surfaces representing streamlines in the fan wheel are used as a basis for design.

Abstract: A blade of the fan wheel of a diagonal-flow fan, which blade should ideally have a shape of a twisted double curvature or undevelopable surface, is formed from a portion of a cylinder, which has a single-curvature or developable surface. To realize the formation of a blade from the single-curvature surface, lines of intersection between a cylinder and a number of coaxial imaginary conical surfaces representing streamlines in the fan wheel are used as a basis for design.

Abstract: A reset circuit used for resetting, for example a memory device after a reading-out from a memory is effected, comprises fist and second reset transistors, for connecting first and second circuits to a common voltage source, and a short-circuit transistor, having a lower threshold voltage than the threshold voltage of said first and second reset transistors, for connecting said first and second circuits when said short circuit transistor receives the same input signal as supplied to said first and second reset transistors.

Abstract: A semiconductor memory device having flip-flop circuits, in which first and second bit lines are connected to each of the flip-flop circuits as a sense amplifier, the potential of the second bit line being opposite to the potential of the first bit line, and the first and second data bus lines cross perpendicularly to the first and second bit lines, respectively, the first and second dummy lines are arranged in parallel with the first and second data bus lines respectively, in order to prevent erroneous operation of an I/O amplifier connected to the first and second data bus lines.

Abstract: A decoder circuit including: a charge-up transistor for maintaining the content of an input address signal; a power supply switching transistor for controlling a charge-up current which is supplied to the charge-up transistor; a predetermined number of selection transistors which are connected at a connection point between the charge-up transistor and the power supply switching transistor so as to select an output word line, and; a bootstrap transistor which is connected to an opposite side of the connection point with respect to the charge-up transistor. The present invention enables the driving of the charge-up transistor with clock pulses having a potential level higher than the power supply line voltage V.sub.DD. The present invention also enables the driving of the power supply switching transistor by clock pulses having a potential level higher than V.sub.DD +V.sub.th wherein V.sub.+h equals the threshold voltage of the power supply switching transistor.