Abstract: The present invention is a DLL circuit, which delays a first clock, and generates a control clock having a predetermined phase relation with this first clock. The DLL circuit comprises a variable delay circuit for varying the delay of the first clock; a phase comparator for comparing the phases of the first clock against that of a second clock, generated by delaying for a predetermined time the output of the variable delay circuit, and for generating a phase comparison result signal; and a delay control circuit for supplying to the variable delay circuit a delay control signal, which controls this delay quantity in response to the phase comparison result signal.

Abstract: A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.

Abstract: An image forming apparatus includes reading means for converting image light obtained by optically scanning an original into an electric signal. An image signal conversion table converts the image signal from the reading means in response to a property of the image forming system. An image signal generating device generates a reference image signal, and an image forming device forms an image on a recording sheet in response to the image signal. The image is formed on the recording sheet by the image forming device in response to the image signal generated by the image signal generating device, and image light obtained by optically scanning the recording sheet is converted into an image signal by the reading device, and the image signal conversion table is corrected on the basis of the image signal converted by the reading device.

Abstract: A method for purifying an exhaust gas by contacting the exhaust gas with an exhaust gas-purifying catalyst comprising a nitrogen oxide-removing catalyst and an adsorbent for ethylene comprising a zeolite which contains Ag, and also Pd, optionally which has a ferrierite structure.

Abstract: A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.

Abstract: A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.

Abstract: An adsorbent for ethylene, comprising a zeolite which contains Ag and which has a ferrierite structure with a SiO.sub.2 /Al.sub.2 O.sub.3 molar ratio being at least 15.

Abstract: A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state.

Abstract: Disclosed is a process for preparing a solid titanium catalyst component, comprising contacting (a) a liquid magnesium compound, (b) a liquid titanium compound, (c) an electron donor and (d) a solid divalent metallic halide. In this process, the solid divalent metallic halide is one having a crystalline structure of the cadmium chloride type. The contact of the component (a) with the component (b) is preferably carried out in the presence of the solid divalent metallic halide (d). According to this process, there can be obtained a solid titanium catalyst component capable of polymerizing olefins with an extremely high activity and capable of producing polyolefins of high stereoregularity when .alpha.-olefins of 3 or more carbon atoms are polymerized.

Abstract: In a semiconductor memory device operable in synchronism with a clock signal externally supplied thereto, there are provided a first part which detects a state of a predetermined signal after a given command is input to the semiconductor memory; and a second part which sets, on the basis of the state of the predetermined signal, the semiconductor memory device to a self-refresh mode in which a refresh operation is carried out without an external signal.

Abstract: A catalyst for purifying an exhaust gas to remove nitrogen oxides, carbon monoxide and hydrocarbons from an oxygen rich exhaust gas containing the same, comprising (i) a zeolite having an SiO.sub.2 /Al.sub.2 O.sub.3 mole ratio of at least 15 and (ii) (a) silver and, optionally, (b) an alkali metal and/or an alkaline earth metal incorporated therein.

Abstract: A double screen (42) including a cylindrical screen (18) and a conical screen (23) is attached to an upper casing (3) into which a revolution shaft (11) is inserted and is provided with a supply opening (2). A rotary blade 12 is arranged within an annular space (15) having a nearly V-shaped section between the cylindrical screen (18) and the conical screen (23) so as to rotate keeping a desired gap relative to the respective screen surfaces. Since the annular space (15) having the nearly V-shaped section is spaced apart from the revolution shaft (11), the rotary blade (12) rotates at a high circumferential speed even in the bottom portion of the annular space (15).

Abstract: A developing apparatus includes a developer carrying member, disposed opposed to an image bearing member, for carrying a developer; a developing bias voltage applying source for applying a developing bias voltage having an oscillating component to the developer carrying member to develop an electrostatic latent image formed on the image bearing member; wherein10.0.ltoreq.T11/(T11+T12).times.100.ltoreq.90.0,where T11 is a time period of a first step in which an electric field is formed in a direction for directing the developer from the developer carrying member toward the image bearing member in one cycle of the oscillating component of the developing bias voltage applied by the developing bias application source, and T12 is a time period of a third step between the first step and a second step in which an electric field is formed in a direction for directing the developer from the image bearing member to the developer carrying member, and T11/(T11+T12) is an inclination of the developing bias voltage.

Abstract: The present invention relates to a word driver circuit provided in a memory circuit. The word driver circuit comprises a P channel and an N channel transistor having a gate electrode commonly connected and one source or drain electrode commonly connected. The N channeltransistor has another source or drain electrode connected to a ground. A word line is connected to the commonly connected source or drain electrode of the transistors. A first selection signal, generated by decoding a first group of address signals, whose potential is either a first potential by which the N channel transistor is rendered conductive or a second potential lower than the first power supply is supplied to the gate electrodes. And a second selection signal, generated by decoding a second group of address signals, whose potential is either a third potential of the selected word line or a fourth potential equal or lower than the first power supply is supplied to another source or drain of the P transistor.

Abstract: A semiconductor memory device includes: a memory cell array having a plurality of word lines; a decoder circuit for decoding an address signal to thereby generate a word line activation signal for driving a corresponding one of the plurality of word lines; a data compression circuit for carrying out a comparison between each data bit, read from the memory cell array in a test mode, of a plurality of memory cells connected to an identical word line, and compressing the result of the comparison to thereby output a logic judgement result; and an output control circuit responsive to an external test mode activation signal and the word line activation signal from the decoder circuit, for controlling the data compression circuit to output the logic judgement result based on the comparison result.

Abstract: A toner for electrophotography, comprising toner particles and an additive, is obtained by mixing toners A and B together which are obtained by respectively adding the additive to each of at least two toner particle groups (a) and (b) having different particle size distributions. The average particle size of the toner particle group (a) is smaller than that of the toner particle group (b), and the amount of additive in the toner A is larger than that in the toner B. The toner reduces the differences in development conditions between different particle sizes due to broadening of toner particle size distribution, thereby enabling a stable image quality to be obtained which maintains a high image density for an extended period of time and is relatively free from fog generation in non-image portions.

Abstract: A semiconductor memory device includes a plurality of memory cell arrays and a plurality of word lines and bit lines. The semiconductor memory device has a plurality of row driving circuits for simultaneously activating a plurality of word lines, and a plurality of column driving circuits for simultaneously and independently activating a plurality of column selection lines to simultaneously select a plurality of bit lines. A data selector selects, from the memory cells selected by the word and bit lines, a memory cell selected by different word lines and bit lines. Thus, a plurality of bits are read out or written into the memory cell arrays in parallel.

Abstract: A catalyst for purifying an exhaust gas to remove nitrogen oxides, carbon monoxide and hydrocarbons from an oxygen-rich exhaust gas containing nitrogen oxides, carbon monoxide and hydrocarbons, comprising (i) a zeolite having an SiO.sub.2 /Al.sub.2 O.sub.3 mole ratio of at least 15 and (ii) (a) cobalt, (b) an alkaline earth metal and (c) silver, or nickel and/or zinc, or platinum and/or manganese, or copper and/or rhodium, incorporated thereinto.

Abstract: A semiconductor integrated circuit device includes a voltage drop circuit for generating a dropped voltage from a power supply voltage externally supplied to a power supply line, and a plurality of circuits respectively connected to the voltage drop circuit and driven by the dropped voltage. A switching unit, which is connected to at least one of the circuits, connects the power supply line to the above one of the circuits in synchronism with operation of the above one of the circuits. The above one of the circuits is driven by currents from both the voltage drop unit and the power supply line in synchronism with the operation thereof.

Abstract: A semiconductor integrated circuit device includes a voltage drop circuit for generating a dropped voltage from a power supply voltage externally supplied to a power supply line, and a plurality of circuits respectively connected to the voltage drop circuit and driven by the dropped voltage. A switching unit, which is connected to at least one of the circuits, connects the power supply line to the above one of the circuits in synchronism with operation of the above one of the circuits. The above one of the circuits is driven by currents from both the voltage drop unit and the power supply line in synchronism with the operation thereof.