Abstract: A semiconductor memory device comprising: (A) a global line; (B) a memory array having (i) a local line, (ii) a decoder connected to the global line and the local line, and (iii) a memory block and a redundant block each constructed by a plurality of memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional unit formed on both sides of the gate electrode and having the function of retaining charges, the memory array having the function that when the decoder is usable, the global line is selectively connected to one of the local lines in accordance with address information and, when a defective block is included in the memory blocks and the decoder is unusable, the local line is separated from the global line and the defective block is replaced with the redundan

Abstract: This invention is a method of improving a data retention ability of a semiconductor memory device having a plurality of nonvolatile memory cells storing a plurality of memory states. The method includes the steps of: (a) selecting the nonvolatile memory cells in a first memory group each of which accumulates charges higher in level than a first threshold from the plurality of nonvolatile memory cells; (b) extracting the nonvolatile memory cells in a first sub-group each of which accumulates the charges lower in level than a second threshold from the nonvolatile memory cells in the first memory group; and (c) programming the nonvolatile memory cells in the first sub-group until each of the nonvolatile memory cells accumulates the charges higher in level than the second threshold.

Abstract: A semiconductor memory device has a malfunction prevention device and a nonvolatile memory.

Abstract: The present invention provides a method of programming, into a computer, a memory array having a plurality of memory cells, including a verification step 1 of verifying whether a memory cell has been already programmed or it has not been programmed yet per memory cell to be programmed, a flagging step 2 of flagging the memory cell in the case where it is verified that the memory cell has not been programmed yet in the several verifying steps, to which the memory cell is subjected thereafter, even if it is verified that the memory cell has been already programmed, a first application step 3 of applying a programming pulse having a programming level to the not-programmed memory cell without any flag, a repeat step 4 of repeating the verification step 1, the flagging step 2 and the first application step 3 until it is verified that all of the memory cells have been already programmed at least once, and a second application step 5 of applying a boost pulse having a boost programming level lower than that of the p

Abstract: A method for driving a semiconductor memory device includes a memory array having a plurality of memory cells arranged in rows and columns. Each memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a source and a drain as diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges. The method includes the steps of: selecting a row line connected to the gate electrode of a memory cell to be selected; grounding a first column line connected to the source of the memory cell to be selected; and applying a first potential to a second column line and a second potential to a third column line at the same time.

Abstract: A semiconductor memory device of the present invention includes an electrically programmable and erasable nonvolatile memory device which uses a plurality of memory cells requiring a first potential for reading data and a second potential for data programming, the second potential being higher than the first potential, a latch circuit for receiving data and temporarily storing the data, a pulse generator which generates a pulse used for programming data into a memory cell and is coupled in order to receive the second potential, a comparator for comparing data in the latch circuit with data in a memory cell, and a controller for controlling the pulse generator to repeatedly generate a pulse until the data in the latch circuit matches the data in the memory cell, the controller coupled to the comparator and the pulse generator. The controller controls so that the pulse is repeatedly generated until data is programmed in a memory cell.

Abstract: A computer system comprising: (A) a CPU; (B) a memory arrangement comprising: (i) a side-wall memory array including a plurality of side-wall memory transistors; (ii) a charge pump; (iii) a plurality of switching circuits; and (iv) logic circuitry; and (C) a system bus, wherein each of the side-wall memory transistors comprises: a gate electrode formed on a semiconductor layer with a gate insulating film formed on the semiconductor layer; a channel region formed below the gate electrode; a pair of diffusion regions formed on the both sides of the channel region and having a conductive type opposite to that of the channel region; and a pair of memory functional units formed on the both sides of the gate electrode and having a function of retaining charges.

Abstract: A semiconductor storage device has a variable-stage charge pump, and a memory cell array to which an output from an output line of the variable-stage charge pump is fed. In the variable-stage charge pump, first and second charge pumps are connected in parallel between a common input bus and a common output bus. A first n-channel MOSFET is provided on a line connecting an output terminal of the first charge pump and the common output bus, and another n-channel MOSFET is provided on a line connecting the second charge pump and the common output bus. First switches are provided between the output terminal of the first charge pump and the first n-channel MOSFET, and between the input terminal of the second charge pump and the second switch. A second switch is provided on a line connecting an input terminal of the second charge pump and the common input bus.

Abstract: A semiconductor storage device includes a voltage supply circuit generating a voltage of 5V, a voltage polarity inversion circuit generating a voltage of −5V, a select-and-connect circuit supplying the voltages of 5V and −5V to a memory cell array, a 5 V voltage level detection circuit detecting the voltage derived from the voltage supply circuit, and a −5 V voltage level detection circuit detecting the voltage derived from the voltage polarity inversion circuit. Absolute values of the voltages detected by the voltage level detection circuits are lower than ever before. This allows a gate insulation film to be thinner. A memory-function film is formed on both sides of a gate electrode in the semiconductor storage device. This also make the gate insulation film thinner. The thin gate insulation film suppresses the short-channel effect, so that each memory element of the memory cell array is miniaturized.

Abstract: A semiconductor memory device including: a memory cell having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges; and an amplifier, the memory cell and the amplifier being connected to each other so that an output of the memory cell is inputted to the amplifier.

Abstract: A nonvolatile semiconductor memory device of the present invention includes: a first booster circuit for generating a first voltage higher than a voltage supplied by an external power source, the first booster circuit being used for writing or deleting of data; a second booster circuit for generating a second voltage higher than the voltage supplied by the external power source, the second booster being used for reading of data; a regulator for controlling the first voltage, the regulator being connected to an output terminal of the first booster circuit; and a reference voltage generator circuit for generating a reference voltage input to the regulator.

Abstract: A nonvolatile semiconductor memory device of the present invention includes: a first booster circuit for generating a first voltage higher than a voltage supplied by an external power source, the first booster circuit being used for writing or deleting of data; a second booster circuit for generating a second voltage higher than the voltage supplied by the external power source, the second booster being used for reading of data; a regulator for controlling the first voltage, the regulator being connected to an output terminal of the first booster circuit; and a reference voltage generator circuit for generating a reference voltage input to the regulator.

Abstract: A non-volatile semiconductor memory device of the present invention includes a plurality of memory cell array blocks on a single integrated circuit. Each of the blocks includes non-volatile memory transistors capable of electrically writing, erasing, and reading information, the transistors being arranged in a matrix, and sources of all of the transistors being commonly connected; a plurality of word lines for commonly connecting control gates of the transistors in each identical row of the matrix; a plurality of bit lines for commonly connecting drains of the transistors in each identical column of the matrix; wherein the plurality of word lines of each of the blocks are respectively connected to the corresponding word lines in an adjacent block through a group of switching transistors provided between the blocks.

Abstract: In a semiconductor memory device, a data holding unit is disposed separately from the first and second floating gate transistors. A voltage difference is generated by the difference between the threshold voltages of the first and second floating gate transistors, and the voltage difference is stored in the form of a binary data. Thereafter, the first and second floating gate transistors are turned off. Thus, a minute current which always flows through the first and second floating gate transistors in the conventional technique is prevented from being generated so that the power consumption is reduced. In addition, data is fetched from the data holding unit while the bias voltage generating units are turned off. Thus, the time period of operating the bias voltage generating units is eliminated so that the memory device can operate at a high speed.

Abstract: A data string representing the initial value (00000000) is supplied to an internal address generator. The internal address initial setting load signal is input to cause the internal address generator to be initialized. Then, a first detection signal is read out from the first detection circuit, and the level of the signal is checked. If the level of the first detection signal is HIGH, it indicates that the initialization of the internal address generator has been conducted normally. If the level of the first detection signal is LOW, it indicates that the initialization of the internal address generator has not been conducted normally. Thereafter, the count-up operation of the internal address generator is conducted while a count-up signal is supplied a predetermined number of times (255 times) to the internal address generator. A second detection signal is read out from a second detection circuit, and the level of the signal is checked.

Abstract: A semiconductor memory is provided to which external data can be written during a self-refresh. Data thus written can be read out and examined to measure the oscillation frequency of the internal refresh oscillator There is no need to use special equipment such as a frequency counter for testing the oscillation frequency, and the oscillation frequency can be tested after chip sealing.

Abstract: There is provided a test method for a semiconductor memory device which can be applied to a margin test, for example. The memory device has two types of sense amplifiers each composed of a layout pattern symmetrical to the other and arrayed such that the layout patterns alternate, memory cells, bit lines which are connected to the sense amplifiers and which carry signals expressing data stored in the memory cells, work lines, gates connected to bit lines, and a comparator which receives signals on bit lines via the gates and determines whether or not the signals match.

Abstract: A pulse generating unit including a delay unit for delaying an input signal of the pulse generating unit and a comparator unit for comparing an output signal of the delay unit with the above mentioned input signal, wherein the delay unit comprises one inverter for inverting the above mentioned input signal and for delaying the pulse fall time of the pulse fall edge of the inverted input signal, whereby the pulse generator generates an output pulse signal with a constant pulse duration even in the case where the pulse duration of the input pulse signal is shorter than the delay time of the delay unit.

Abstract: A semiconductor memory device of the type with a plurality of bit line pairs and signal lines disposed parallel to these bit line pairs is characterized in that two bit lines forming a pair are crossed at least once in the middle to prevent capacitance imbalance caused by misalignment of the associated signal line.

Abstract: A semiconductor device such as a DRAM with many signal line circuits is also provided with a redundancy circuit and is so structured that when one of the signal line circuits is defective and the fuse contained by such a defective signal line circuit is cut off to inactivate it, an input signal which would select the inactivated signal line circuit will automatically select the redundancy circuit.