Patents by Inventor Masaru Nawaki

Masaru Nawaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4757218
    Abstract: A semiconductor IC device has word lines which are sequentially arranged and each connected to the gate of a MOS transistor such that its drain and source are individually connected to the adjacent word lines. Either of these adjacent word lines is connected to a fixed potential source such that potential changes in selected one of these word lines are electrically shielded and do not affect the non-selected other word lines in the device.
    Type: Grant
    Filed: January 8, 1987
    Date of Patent: July 12, 1988
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masaru Nawaki
  • Patent number: 4670765
    Abstract: A semiconductor photodetector element has a three-dimensional multi-layer structure including a photoconductive layer for photoelectric conversion, a layer for binary conversion and amplification and a layer including a redundancy circuit so that the need for external reset and clock inputs can be obviated and correct image information can be expected even if there are defective cells among the photodetection conversion cells.
    Type: Grant
    Filed: March 26, 1985
    Date of Patent: June 2, 1987
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tutomu Nakamura, Masaru Shiraishi, Masaru Nawaki