Patents by Inventor Masaru Sawada
Masaru Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8339206Abstract: A PLL includes: a charge-pump equalizer which has a plurality of charge pumps generating charge currents according to phase-difference signals, each being generated by delaying the phase-difference signal by different times, adds and outputs the charge currents generated by the charge pumps; a replica circuit, having ideal characteristics of a loop filter and a voltage controlled oscillator, which input a digital value having phase difference of the phase-difference signals, and generates a replica output according to the ideal characteristics; and a coefficient generating circuit which smoothes correlation values of the difference signals and the phase-difference signals to generate charge pump coefficients, and negatively feeds back the same to the plurality of charge pumps. The charge pumps generate the charge currents each having current values corresponding to the charge pump coefficients.Type: GrantFiled: December 2, 2011Date of Patent: December 25, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Masaru Sawada
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Publication number: 20120218049Abstract: A PLL includes: a charge-pump equalizer which has a plurality of charge pumps generating charge currents according to phase-difference signals, each being generated by delaying the phase-difference signal by different times, adds and outputs the charge currents generated by the charge pumps; a replica circuit, having ideal characteristics of a loop filter and a voltage controlled oscillator, which input a digital value having phase difference of the phase-difference signals, and generates a replica output according to the ideal characteristics; and a coefficient generating circuit which smoothes correlation values of the difference signals and the phase-difference signals to generate charge pump coefficients, and negatively feeds back the same to the plurality of charge pumps. The charge pumps generate the charge currents each having current values corresponding to the charge pump coefficients.Type: ApplicationFiled: December 2, 2011Publication date: August 30, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Masaru SAWADA
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Patent number: 8244188Abstract: A transmitting and receiving circuit includes a transmitting side amplifier circuit amplifying a transmission signal transmitted from an antenna, a receiving side amplifier circuit amplifying a reception signal received by the antenna and being electrically connected to the a transmitting side amplifier circuit, a first matching circuit matching the antenna and the transmitting side amplifier circuit, a second matching circuit matching the antenna and the receiving side amplifier circuit, a first current source circuit capable of controlling an operating state and setting a first connection point between the first matching circuit and an output terminal of the transmitting side amplifier circuit to a given voltage, and a second current source circuit capable of controlling an operating state and setting a second connection point between the second matching circuit and an input terminal of the receiving side amplifier circuit to a given voltage.Type: GrantFiled: January 22, 2010Date of Patent: August 14, 2012Assignee: Fujitsu LimitedInventors: Masaru Sawada, Hideaki Kondo, Norio Murakami
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Publication number: 20100120375Abstract: A transmitting and receiving circuit includes a transmitting side amplifier circuit amplifying a transmission signal transmitted from an antenna, a receiving side amplifier circuit amplifying a reception signal received by the antenna and being electrically connected to the a transmitting side amplifier circuit, a first matching circuit matching the antenna and the transmitting side amplifier circuit, a second matching circuit matching the antenna and the receiving side amplifier circuit, a first current source circuit capable of controlling an operating state and setting a first connection point between the first matching circuit and an output terminal of the transmitting side amplifier circuit to a given voltage, and a second current source circuit capable of controlling an operating state and setting a second connection point between the second matching circuit and an input terminal of the receiving side amplifier circuit to a given voltage.Type: ApplicationFiled: January 22, 2010Publication date: May 13, 2010Applicant: FUJITSU LIMITEDInventors: Masaru SAWADA, Hideaki KONDO, Norio MURAKAMI
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Patent number: 7697030Abstract: A monitor camera is provided with a control device which carries out a predetermined process in response to an input of a trigger signal. The control device has an arrangement in that continuous images are successively inputted from a camera unit thereto and in that a detection of a moving object is carried out by detecting a change in images in a moving-object detector. When no change in images is detected by the moving-object detector within a predetermined time after the input of a trigger signal from a detection sensor to a trigger signal input unit, the control device determines the trigger signal inputted to the trigger signal input unit as valid. Then, only when the valid trigger signal has been detected, an abnormality process is carried out. Consequently, it is possible to prevent the abnormality process from being performed upon erroneous detection of a normal state as an abnormal state.Type: GrantFiled: December 10, 2003Date of Patent: April 13, 2010Assignee: Konica Minolta Holdings, Inc.Inventors: Tomoyuki Terada, Masaru Sawada, Naotaka Kishida, Ayumi Itoh
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Patent number: 7619465Abstract: A filter circuit includes a low-pass filter and a calibration circuit calibrating a frequency characteristic of the low-pass filter. The calibration circuit includes a negative feedback circuit and a control circuit.Type: GrantFiled: May 22, 2008Date of Patent: November 17, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Hideaki Kondo, Masaru Sawada, Norio Murakami, Syoichi Masui
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Patent number: 7515369Abstract: A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.Type: GrantFiled: March 24, 2006Date of Patent: April 7, 2009Assignee: Fujitsu LimitedInventors: Takao Sugawara, Motomu Takatsu, Masaru Sawada
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Publication number: 20080297240Abstract: A filter circuit includes a low-pass filter and a calibration circuit calibrating a frequency characteristic of the low-pass filter. The calibration circuit includes a negative feedback circuit and a control circuit.Type: ApplicationFiled: May 22, 2008Publication date: December 4, 2008Applicant: FUJITSU LIMITEDInventors: Hideaki Kondo, Masaru Sawada, Norio Murakami, Syoichi Masui
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Patent number: 7385533Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.Type: GrantFiled: July 10, 2006Date of Patent: June 10, 2008Assignee: Fujitsu LimitedInventors: Masaru Sawada, Toshio Ito, Toshihiko Morita
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Patent number: 7286596Abstract: In a training operation for optimizing a multiplication coefficient for each tap of an FIR equalizer equalizing a read signal read from a recording medium, as a restricted coefficient updating vector applied for updating the multiplication coefficient for each tap of an FIR filter, a vector is utilized which is obtained by projecting, onto a plane perpendicular to a predetermined restricting conditioning vector, a coefficient updating vector determined based on an equalizer error between the output of the FIR equalizer and a reproduction output determined therefrom and a delayed input value for each tap of the FIR equalizer.Type: GrantFiled: November 26, 2003Date of Patent: October 23, 2007Assignee: Fujitsu LimitedInventors: Masaru Sawada, Motomu Takatsu, Takao Sugawara
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Patent number: 7248188Abstract: An encoded-bit-string generating unit generates a bit string encoded by scrambling an input bit string. A direct-current-component evaluating unit selects a bit string having a predetermined width in the bit string generated by the encoded-bit-string generating unit, while shifting bits one by one, and evaluates the direct-current component in the selected bit string. A bit-string extracting unit extracts a bit string with suppressed direct-current component, based on a result of an evaluation by the direct-current-component evaluating unit.Type: GrantFiled: March 16, 2006Date of Patent: July 24, 2007Assignee: Fujitsu LimitedInventors: Toshio Ito, Masaru Sawada, Toshihiko Morita
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Patent number: 7138931Abstract: A recording and reproducing apparatus includes an RLL encoder that encodes an information bit string to a code bit string and a RLL decoder that decodes the code bit string to the information bit string. The RLL encoder encodes the information bit string to the code bit string of a run-length-limited code at a high encoding rate satisfying a plurality of conditions of constraint regarding a string of successive zeros. The RLL decoder decodes the code bit string encoded by the RLL encoder to the information bit string.Type: GrantFiled: November 5, 2004Date of Patent: November 21, 2006Assignee: Fujitsu LimitedInventors: Toshio Ito, Masaru Sawada, Toshihiko Morita, Takao Sugawara
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Publication number: 20060250286Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.Type: ApplicationFiled: July 10, 2006Publication date: November 9, 2006Inventors: Masaru Sawada, Toshio Ito, Toshihiko Morita
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Publication number: 20060220928Abstract: An encoded-bit-string generating unit generates a bit string encoded by scrambling an input bit string. A direct-current-component evaluating unit selects a bit string having a predetermined width in the bit string generated by the encoded-bit-string generating unit, while shifting bits one by one, and evaluates the direct-current component in the selected bit string. A bit-string extracting unit extracts a bit string with suppressed direct-current component, based on a result of an evaluation by the direct-current-component evaluating unit.Type: ApplicationFiled: March 16, 2006Publication date: October 5, 2006Inventors: Toshio Ito, Masaru Sawada, Toshihiko Morita
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Publication number: 20060220926Abstract: An encoder includes an encoded-bit-string generating unit that generates a plurality of bit strings encoded by scrambling with respect to an input bit string; a DC-component evaluating unit that selects a bit string having a predetermined width in the bit strings generated by the encoded-bit-string generating unit, while shifting bits one by one or every m-bits, where m is a positive integer, and evaluates the DC component in each of the bit strings selected; and a bit-string extracting unit that extracts a bit string with suppressed DC component from among the bit strings encoded, based on a result of an evaluation by the direct-current-component evaluating unit.Type: ApplicationFiled: August 11, 2005Publication date: October 5, 2006Inventors: Toshio Ito, Masaru Sawada, Toshihiko Morita
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Patent number: 7098818Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.Type: GrantFiled: June 24, 2005Date of Patent: August 29, 2006Assignee: Fujitsu LimitedInventors: Masaru Sawada, Toshio Ito, Toshihiko Morita
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Publication number: 20060181797Abstract: A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.Type: ApplicationFiled: March 24, 2006Publication date: August 17, 2006Inventors: Takao Sugawara, Motomu Takatsu, Masaru Sawada
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Patent number: 7054088Abstract: A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.Type: GrantFiled: October 18, 2002Date of Patent: May 30, 2006Assignee: Fujitsu LimitedInventors: Akihiro Yamazaki, Takao Sugawara, Motomu Takatsu, Masaru Sawada
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Patent number: 7035029Abstract: An information recording/reading apparatus employs a preamble to reproduce a clock used when recording information in a recording medium and reads the information out of the recording medium at a timing synchronized with a read signal. The preamble is split and recorded by replacing a middle portion of the preamble with data and a sync byte. While a first buffer is employed to delay signal data read out of the recording medium, a frequency offset detector detects a frequency offset using the split preamble.Type: GrantFiled: February 11, 2004Date of Patent: April 25, 2006Assignee: Fujitsu LimitedInventors: Masaru Sawada, Toshihiko Morita, Takao Sugawara
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Patent number: 7023946Abstract: A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.Type: GrantFiled: November 6, 2002Date of Patent: April 4, 2006Assignee: Fujitsu LimitedInventors: Masaru Sawada, Tsuyoshi Tomita, Yoshitaka Nakata, Tsunehiko Moriuchi, Kenichi Yamakura, Hideaki Tanishima, Fumiaki Uematsu, Koji Horibe, Manabu Nakano