Patents by Inventor Masaru Sawada
Masaru Sawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050225458Abstract: A recording and reproducing apparatus includes an RLL encoder that encodes an information bit string to a code bit string and a RLL decoder that decodes the code bit string to the information bit string. The RLL encoder encodes the information bit string to the code bit string of a run-length-limited code at a high encoding rate satisfying a plurality of conditions of constraint regarding a string of successive zeros. The RLL decoder decodes the code bit string encoded by the RLL encoder to the information bit string.Type: ApplicationFiled: November 5, 2004Publication date: October 13, 2005Inventors: Toshio Ito, Masaru Sawada, Toshihiko Morita, Takao Sugawara
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Publication number: 20050099907Abstract: In a training operation for optimizing a multiplication coefficient for each tap of an FIR equalizer equalizing a read signal read from a recording medium, as a restricted coefficient updating vector applied for updating the multiplication coefficient for each tap of the FIR filter, a vector is utilized which is obtained by projecting, onto a plane perpendicular to a predetermined restricting conditional vector, a coefficient updating vector determined based on an equalizer error between the output of the FIR equalizer and a reproduction output determined therefrom and a delayed input value for each tap of the FIR equalizer.Type: ApplicationFiled: November 26, 2003Publication date: May 12, 2005Applicant: FUJITSU LIMITEDInventors: Masaru Sawada, Motomu Takatsu, Takao Sugawara
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Publication number: 20050030376Abstract: A monitor camera is provided with a control device which carries out a predetermined process in response to an input of a trigger signal. The control device has an arrangement in that continuous images are successively inputted from a camera unit thereto and in that a detection of a moving object is carried out by detecting a change in images in a moving-object detector. When no change in images is detected by the moving-object detector within a predetermined time after the input of a trigger signal from a detection sensor to a trigger signal input unit, the control device determines the trigger signal inputted to the trigger signal input unit as valid. Then, only when the valid trigger signal has been detected, an abnormality process is carried out. Consequently, it is possible to prevent the abnormality process from being performed upon erroneous detection of a normal state as an abnormal state.Type: ApplicationFiled: December 10, 2003Publication date: February 10, 2005Inventors: Tomoyuki Terada, Masaru Sawada, Naotaka Kishida, Ayumi Itoh
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Patent number: 6798832Abstract: A semiconductor circuit includes a decision feedback equalizer (DFE) for waveform-equalizing an input signal and generating a waveform-equalized input signal. The DFE compares the waveform-equalized signal with a predetermined reference voltage to generate a decision signal having first and second decision values and an error signal which lies between the waveform-equalized signal and the decision signal. A dispersion value calculator is connected to the DFE, calculates first and second dispersion values of the first and second decision values of the decision signal using the error signal, and produces a compensation signal using the first and second dispersion values. An asymmetry compensator is connected to the DFE and the dispersion value calculator. The asymmetry compensator receives the input signal and corrects an asymmetry in the input signal in accordance with the compensation signal and supplies the corrected input signal to the DFE.Type: GrantFiled: March 27, 2000Date of Patent: September 28, 2004Assignee: Fujitsu LimitedInventors: Yoshitaka Nakata, Masaru Sawada, Tsunehiko Moriuchi
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Publication number: 20040179287Abstract: An information recording/reading apparatus employs a preamble to reproduce a clock used when recording information in a recording medium and reads the information out of the recording medium at a timing synchronized with a read signal. The preamble is split and recorded by replacing a middle portion of the preamble with data and a sync byte. While a first buffer is employed to delay signal data read out of the recording medium, a frequency offset detector detects a frequency offset using the split preamble.Type: ApplicationFiled: February 11, 2004Publication date: September 16, 2004Applicant: FUJITSU LIMITEDInventors: Masaru Sawada, Toshihiko Morita, Takao Sugawara
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Publication number: 20040003411Abstract: An image service system includes an imaging unit for capturing an image of an object; and a server for storing a plurality of images captured by the imaging unit and selecting one or more desired images from the stored images. The server transmits the selected images or information associated with the selected images via a network to a terminal.Type: ApplicationFiled: June 27, 2003Publication date: January 1, 2004Applicant: MINOLTA CO., LTD.Inventors: Masaaki Nakai, Yuichi Kawakami, Tomoyuki Terada, Masaru Sawada, Natsuko Shiota, Naotaka Kishida, Ayumi Itoh, Shinji Sakai
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Patent number: 6671112Abstract: A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The a control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.Type: GrantFiled: December 21, 2001Date of Patent: December 30, 2003Assignee: Fujitsu LimitedInventors: Hiroko Murakami, Masaru Sawada, Manabu Nakano, Kazuyoshi Kikuta
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Patent number: 6671115Abstract: A servo signal processing apparatus for processing a servo signal corresponding to servo information from a servo area on a recording medium for controlling a head. The servo area includes a servo mark area for storing a servo mark indicative of a head of the servo area, a gray mark area for storing a gray mark indicative of a head of information for position control for the head, and a gray code area for storing information. An A-D converter converts the servo signal to digital data. A digital filter filters the converted data based on a sampling clock, and outputs the filtered digital data. A servo mark detector detects a servo mark based on a continuity of a first predetermined logical value. A gray code decoder detects a gray code based on a continuity of a predetermined logical value. The gray code decoder decodes information stored in a gray code area following the detected gray mark.Type: GrantFiled: March 15, 2000Date of Patent: December 30, 2003Assignee: Fujitsu LimitedInventors: Hiroko Haraguchi, Masaru Sawada
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Patent number: 6600779Abstract: A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.Type: GrantFiled: March 23, 1999Date of Patent: July 29, 2003Assignee: Fujitsu LimitedInventors: Masaru Sawada, Tsuyoshi Tomita, Yoshitaka Nakata, Tsunehiko Moriuchi, Kenichi Yamakura, Hideaki Tanishima, Fumiaki Uematsu, Koji Horibe, Manabu Nakano
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Publication number: 20030137765Abstract: A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. Therefore, the timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. After that, while the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.Type: ApplicationFiled: October 18, 2002Publication date: July 24, 2003Applicant: FUJITSU LIMITEDInventors: Akihiro Yamazaki, Takao Sugawara, Motomu Takatsu, Masaru Sawada
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Publication number: 20030088834Abstract: A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The a control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.Type: ApplicationFiled: December 21, 2001Publication date: May 8, 2003Inventors: Hiroko Murakami, Masaru Sawada, Manabu Nakano, Kazuyoshi Kikuta
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Publication number: 20030058930Abstract: A signal processor used to process an analog read signal representing data stored on a magnetic disk allows for a faster read operation without requiring an increase in its circuit area or buffer memory space. The signal processor includes a decision feedback equalizer which selectively provides a feedback signal added to a read signal in reproducing data read from a storage medium. The signal processor also performs error correction. In performing error correction, the load of the error correcting process is detected and the processing speed is altered depending upon the detected load.Type: ApplicationFiled: November 6, 2002Publication date: March 27, 2003Applicant: Fujitsu, Ltd.Inventors: Masaru Sawada, Tsunehiko Moriuchi
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Publication number: 20030007273Abstract: A servo signal processing apparatus for processing a servo signal corresponding to servo information from a servo area on a recording medium for controlling a head. The servo area includes a servo mark area for storing a servo mark indicative of a head of the servo area, a gray mark area for storing a gray mark indicative of a head of information for position control for the head, and a gray code area for storing information. An A-D converter converts the servo signal to digital data. A digital filter filters the converted data based on a sampling clock, and outputs the filtered digital data. A servo mark detector detects a servo mark based on a continuity of a first predetermined logical value. A gray code decoder detects a gray code based on a continuity of a predetermined logical value. The gray code decoder decodes information stored in a gray code area following the detected gray mark.Type: ApplicationFiled: March 15, 2000Publication date: January 9, 2003Inventors: Hiroko Haraguchi, Masaru Sawada
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Patent number: 6288665Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.Type: GrantFiled: May 9, 2000Date of Patent: September 11, 2001Assignee: Fujitsu LimitedInventors: Sanroku Tsukamoto, Ian Dedic, Kuniyoshi Kamei, Toshiaki Endo, Masaru Sawada, Hiroko Murakami
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Patent number: 6288668Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.Type: GrantFiled: February 21, 1996Date of Patent: September 11, 2001Assignee: Fujitsu LimitedInventors: Sanroku Tsukamoto, Ian Dedic, Kuniyoshi Kamei, Toshiaki Endo, Masaru Sawada, Hiroko Murakami
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Patent number: 6061311Abstract: A device for reproducing data recorded on a recording medium, such as a magnetic disk or an optical disk, includes a data reading apparatus and a data reproducing apparatus. The data reading apparatus reads sector data from the reading medium, including data, synch-byte signals and control signals, and generates a clock signal. The data reading apparatus reproduces the recorded data in accordance with the clock signal. When a synch-byte signal is detected by the reading apparatus, transmission of control signals to the reproducing apparatus is inhibited. In addition, lost data is recovered using other data and an ECC code.Type: GrantFiled: December 16, 1997Date of Patent: May 9, 2000Assignee: Fujitsu LimitedInventors: Shigetaka Asano, Masaru Sawada
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Patent number: 6052244Abstract: A servo signal processing apparatus for processing a servo signal corresponding to servo information from a servo area on a recording medium for controlling a head. The servo area includes a servo mark area for storing a servo mark indicative of a head of the servo area, a gray mark area for storing a gray mark indicative of a head of information for position control for the head, and a gray code area for storing information. An A-D converter converts the servo signal to digital data. A digital filter filters the converted data based on a sampling clock, and outputs the filtered digital data. A servo mark detector detects a servo mark based on a continuity of a first predetermined logical value. A gray code decoder detects a gray code based on a continuity of a predetermined logical value. The gray code decoder decodes information stored in a gray code area following the detected gray mark.Type: GrantFiled: December 23, 1997Date of Patent: April 18, 2000Assignee: Fujitsu LimitedInventors: Hiroko Haraguchi, Masaru Sawada
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Patent number: 6046694Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.Type: GrantFiled: February 21, 1996Date of Patent: April 4, 2000Assignee: Fujitsu LimitedInventors: Sanroku Tsukamoto, Ian Dedic, Kuniyoshi Kamei, Toshiaki Endo, Masaru Sawada, Hiroko Murakami
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Patent number: 5870591Abstract: A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.Type: GrantFiled: August 2, 1996Date of Patent: February 9, 1999Assignee: Fujitsu LimitedInventor: Masaru Sawada
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Patent number: 5848046Abstract: A signal processing circuit converts a serial analog signal, obtained by sequentially reading data recorded on a disk by a head, to a parallel digital signal to be output. The signal processing circuit also converts an externally input parallel digital signal to a serial analog signal at the time of recording data on the disk and sends the analog signal to the head. The signal processing circuit comprises a converter that converts the serial analog signal of data read from the disk to a serial digital signal and converts the parallel digital signal of externally input data to an analog signal in order to send the analog signal to the head. A shift register converts the serial digital signal received from the converter to a parallel digital signal in a data read mode and converts the parallel digital signal externally input to a serial digital signal to send the serial digital signal to the converter in a data write mode.Type: GrantFiled: June 5, 1997Date of Patent: December 8, 1998Assignee: Fujitsu LimitedInventor: Masaru Sawada