Patents by Inventor Masaru Yamada

Masaru Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978612
    Abstract: A plasma processing apparatus includes a processing chamber in which a sample is subjected to plasma processing, a first radio frequency power supply that supplies radio frequency power for generating plasma, a sample stage on which the sample is mounted, and a second radio frequency power supply that supplies radio frequency power to the sample stage, the plasma processing apparatus further includes a DC power supply that applies a DC voltage, that is changed according to a periodically repeated waveform, to the sample stage, and the waveform of one cycle has a period in which amplitude changes by a predetermined amount or more during a predetermined time. Accordingly, charged particles on a wafer surface are removed, a trench shape with high verticality can be obtained, and damage to a film that is not to be etched inside a trench can be reduced.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: May 7, 2024
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Isao Mori, Masaru Izawa, Naoki Yasui, Norihiko Ikeda, Kazuya Yamada
  • Publication number: 20240117082
    Abstract: Even when used in applications such as electronic materials, display materials, and inks, in which required standards in terms of coloring prevention, long term stability, low impurity content, and the like, are extremely high, the present invention can meet such required standards. The present invention addresses the problem of providing an allylamine (co)polymer which overcomes the limitations of the prior art, undergoes little coloring, contains little impurities and exhibits excellent long term stability; and a method for producing the same. This problem can be solved by an allylamine (co)polymer which has constituent units derived from allylamine and contains sulfuric acid groups in the structure thereof, in which the proportion of the sulfuric acid groups with respect to the total mass of the allylamine (co)polymer is 20,000 ppm by mass or less.
    Type: Application
    Filed: December 8, 2023
    Publication date: April 11, 2024
    Applicant: NITTO BOSEKI CO., LTD.
    Inventors: Nobuyuki YAMADA, Masaru BUNYA
  • Patent number: 11920077
    Abstract: No studies have been made regarding what kinds of refrigerants should be used in a refrigeration cycle device for a vehicle. An air conditioner (1) for a vehicle includes a refrigerant circuit (10) and a refrigerant that is sealed in the refrigerant circuit (10). The refrigerant circuit (10) includes a compressor (80), a first heat exchanger (85), which serves as a heat dissipater in a dehumidifying heating mode, an outside-air heat exchanger (82), a cooling control valve (87), and a second heat exchanger (86), which serves as an evaporator in the dehumidifying heating mode. The refrigerant is a refrigerant having a low GWP.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 5, 2024
    Assignee: DAIKIN INDUSTRIES, LTD.
    Inventors: Eiji Kumakura, Kazuhiro Furusho, Masaru Tanaka, Shun Ohkubo, Mitsushi Itano, Yuuki Yotsumoto, Akihito Mizuno, Tomoyuki Gotou, Yasufu Yamada, Tatsumi Tsuchiya, Kenji Gobou, Hitomi Kuroki, Daisuke Karube, Tatsuya Takakuwa, Tetsushi Tsuda
  • Patent number: 11912922
    Abstract: A showcase includes a refrigerant circuit and a refrigerant enclosed in the refrigerant circuit. The refrigerant circuit includes a compressor (121), a radiator (122), an expansion valve (123), and an evaporator (124). The refrigerant is a low-GWP refrigerant.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 27, 2024
    Assignee: DAIKIN INDUSTRIES, LTD.
    Inventors: Shinichi Fujinaka, Masaru Tanaka, Shun Ohkubo, Mitsushi Itano, Yuuki Yotsumoto, Akihito Mizuno, Tomoyuki Gotou, Yasufu Yamada, Hitomi Kuroki, Tatsumi Tsuchiya, Kenji Gobou, Daisuke Karube, Tatsuya Takakuwa
  • Patent number: 10192851
    Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: January 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Miyaki, Masaru Yamada
  • Publication number: 20180323168
    Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.
    Type: Application
    Filed: July 11, 2018
    Publication date: November 8, 2018
    Inventors: Yoshinori MIYAKI, Masaru YAMADA
  • Patent number: 10032745
    Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.
    Type: Grant
    Filed: July 26, 2014
    Date of Patent: July 24, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Miyaki, Masaru Yamada
  • Publication number: 20150031191
    Abstract: To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.
    Type: Application
    Filed: July 26, 2014
    Publication date: January 29, 2015
    Inventors: Yoshinori Miyaki, Masaru Yamada
  • Patent number: 8293157
    Abstract: A method of manufacturing a cellulose/gelatin composite viscose rayon filament that is characterized by including a process in which a spinning process is carried out while a viscose spinning solution is mixed with a gelatin crosslinking solution, which makes it possible to produce a cellulose/gelatin composite viscose rayon having uniform strength and elongation without yarn disconnection.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: October 23, 2012
    Assignee: Kurashiki Boseki Kabushiki Kaisha
    Inventors: Masaru Yamada, Kunihiro Ohshima
  • Patent number: 8084826
    Abstract: An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner, oxygen or the like is ion-implanted. Thereafter, heat treatment is performed to cause shrinkage of the contact liner in the N-channel region to form an n-channel contact liner, and to cause expansion of the contact liner in the P-channel region to form a p-channel contact liner.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: December 27, 2011
    Assignee: Panasonic Corporation
    Inventors: Kenshi Kanegae, Masaru Yamada
  • Patent number: 8034721
    Abstract: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the side wall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: October 11, 2011
    Assignee: Panasonic Corporation
    Inventors: Masaru Yamada, Akihiko Tsudumitani
  • Publication number: 20110001193
    Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.
    Type: Application
    Filed: September 15, 2010
    Publication date: January 6, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
  • Patent number: 7821138
    Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: October 26, 2010
    Assignee: Panasonic Corporation
    Inventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
  • Publication number: 20100159702
    Abstract: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the side wall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.
    Type: Application
    Filed: March 4, 2010
    Publication date: June 24, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Masaru YAMADA, Akihiko Tsudumitani
  • Patent number: 7696099
    Abstract: A first film and a second film are formed on a semiconductor substrate in this order. A resist pattern is formed on the second film. An opening is formed by removing the second film exposed between the resist pattern at a state where the second film remains on the bottom. A first removal preventing film is formed on the side wall of the opening and the residual film is removed at a state where the projecting part of the second film protruding from the sidewall to the opening remains. The first film exposed in the opening is removed. A second removal preventing film is formed on the first removal preventing film and the surface of the semiconductor substrate exposed in the opening is removed at a state where the projecting part of the semiconductor substrate protruding from the side wall to the opening remains and a round part is formed at the projecting part of the semiconductor substrate. The semiconductor substrate exposed in the opening is further removed.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: April 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Masaru Yamada, Akihiko Tsudumitani
  • Publication number: 20090200582
    Abstract: The semiconductor comprises an n-channel transistor forming region and a p-channel transistor forming region, which are disposed while being sectioned by an element isolation region. The stress caused by contact plugs in the n-channel transistor forming region and the stress caused by contact plugs in the p-channel transistor forming region are made different from each other. With this, it enables to increase the drive current of both the n-channel transistor and p-channel transistor without changing the dimensions of the active region and the element isolation region.
    Type: Application
    Filed: March 17, 2009
    Publication date: August 13, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Masaru Yamada, Masafumi Tsutsui, Kiyoyuki Morita
  • Publication number: 20090200615
    Abstract: An element larger than silicon is ion-implanted to a contact liner in an N-channel region to break constituent atoms of the contact liner in the N-channel region. An element larger than silicon is ion-implanted to the contact liner in a P-channel region to break constituent atoms of the contact liner, oxygen or the like is ion-implanted. Thereafter, heat treatment is performed to cause shrinkage of the contact liner in the N-channel region to form an n-channel contact liner, and to cause expansion of the contact liner in the P-channel region to form a p-channel contact liner.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 13, 2009
    Inventors: Kenshi KANEGAE, Masaru YAMADA
  • Publication number: 20090166919
    Abstract: A method of manufacturing a cellulose/gelatin composite viscose rayon filament that is characterized by including a process in which a spinning process is carried out while a viscose spinning solution is mixed with a gelatin crosslinking solution, which makes it possible to produce a cellulose/gelatin composite viscose rayon having uniform strength and elongation without yarn disconnection.
    Type: Application
    Filed: May 10, 2006
    Publication date: July 2, 2009
    Inventors: Masaru Yamada, Kunihiro Ohshima
  • Patent number: 7446015
    Abstract: A semiconductor device includes a circuit formation region which is formed in a semiconductor substrate and includes a plurality of element formation regions surrounded by isolation regions, respectively. A stress effect relief region of a predetermined width is formed around the circuit formation region to relieve a stress effect of the isolation regions on the operation characteristics of elements formed in the element formation regions and a plurality of dummy features are formed in the stress effect relief region and other part of the circuit formation region than the element formation regions at predetermined distances, the dummy features having the same composition as the element formation regions and predetermined planar dimensions.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: November 4, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasutoshi Okuno, Masaru Yamada
  • Publication number: 20070277509
    Abstract: Decreases in the volume of intake air to an engine in response to environmental changes results in an increase in amount of PM emissions. In view of this situation, a correction coefficient of fuel supply interval is calculated based on the variation in amount of PM emissions to adjust a reference fuel supply interval in order to determine an target fuel supply interval. By adjusting the fuel supply interval, a fuel supply amount appropriate to the variation in amount of PM emissions, thereby preventing clogging of the injection hole of a supplemental fuel valve, while maintaining fuel economy.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 6, 2007
    Inventors: Jun Tahara, Masaru Yamada, Tadashi Toyota