Patents by Inventor Masashi Horiguchi
Masashi Horiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140252495Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.Type: ApplicationFiled: February 10, 2014Publication date: September 11, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Nozomu MATSUZAKI, Hiroyuki MIZUNO, Masashi HORIGUCHI
-
Publication number: 20140232476Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Applicant: Renesas Electronics CorporationInventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
-
Patent number: 8736390Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.Type: GrantFiled: December 10, 2011Date of Patent: May 27, 2014Assignee: Rensas Electronics CorporationInventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
-
Publication number: 20140140145Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.Type: ApplicationFiled: January 26, 2014Publication date: May 22, 2014Applicants: HITACHI DEVICE ENGINEERING CO., LTD., RENESAS ELECTRONICS CORPORATIONInventors: Binhaku TARUISHI, Hiroki MIYASHITA, Ken SHIBATA, Masashi HORIGUCHI
-
Patent number: 8674419Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.Type: GrantFiled: July 19, 2010Date of Patent: March 18, 2014Assignee: Renesas Electronics CorporationInventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
-
Publication number: 20140035689Abstract: The present invention provides a semiconductor device including a first terminal and a second terminal respectively coupled to both ends of a crystal resonator, an inverter circuit having an input coupled to the first terminal and an output coupled to the second terminal, a feedback resistor which couples between the first terminal and the second terminal, a variable capacitor coupled to at least one of the first and second terminals, and a control circuit. The control circuit performs control to increase both of the drive capability of the inverter circuit and the capacitance value of the variable capacitor in a second mode rather than a first mode.Type: ApplicationFiled: July 26, 2013Publication date: February 6, 2014Applicant: Renesas Electronics CorporationInventors: Osamu Ozawa, Masashi Horiguchi, Takayasu Ito
-
Patent number: 8644090Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.Type: GrantFiled: June 25, 2013Date of Patent: February 4, 2014Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
-
Publication number: 20140015504Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.Type: ApplicationFiled: April 9, 2012Publication date: January 16, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shinya Sano, Masashi Horiguchi, Takahiro Miki, Mitsuru Hiraki
-
Publication number: 20130328615Abstract: The present invention provides a voltage generation circuit which outputs high-precision output voltage in a wide temperature range. A semiconductor device has a voltage generation circuit. The voltage generation circuit has a reference voltage generation circuit which outputs reference voltage, and a plurality of correction circuits for generating a correction current and making it fed back to the reference voltage generation circuit. The correction circuits generate sub correction currents which monotonously increase from predetermined temperature which varies among the correction circuits toward a low-temperature side or a high-temperature side. The correction current is sum of a plurality of sub correction currents.Type: ApplicationFiled: June 7, 2013Publication date: December 12, 2013Inventors: Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi
-
Publication number: 20130286753Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.Type: ApplicationFiled: June 25, 2013Publication date: October 31, 2013Applicant: HITACHI DEVICE ENGINEERING CO., LTD.Inventors: Binhaku TARUISHI, Hiroki MIYASHITA, Ken SHIBATA, Masashi HORIGUCHI
-
Patent number: 8482991Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.Type: GrantFiled: August 31, 2012Date of Patent: July 9, 2013Assignee: Renesas Electronics CorporationInventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
-
Publication number: 20120327723Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.Type: ApplicationFiled: August 31, 2012Publication date: December 27, 2012Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
-
Publication number: 20120265473Abstract: Improvement in the accuracy of a temperature sensor is aimed at, suppressing the number of the test temperature in a test process. The semiconductor device comprises a coefficient calculation unit which calculates up to the N-th order coefficient (N is an integer equal to or greater than one) of a correction function as an N-th order approximation of a characteristic function indicating correspondence relation of temperature data measured by a temperature sensor unit and temperature, based on N+1 pieces of the temperature data including a theoretical value at a predetermined temperature in the characteristic function and N measured values of the temperature data measured by the temperature sensor unit at N points of temperature; and a correction operation unit which generates data including information on temperature, by performing calculation using the correction function to which the coefficients calculated are applied, based on temperature data measured by the temperature sensor unit.Type: ApplicationFiled: April 4, 2012Publication date: October 18, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Naoya ARISAKA, Takayasu ITO, Masashi HORIGUCHI
-
Patent number: 8264893Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.Type: GrantFiled: September 21, 2011Date of Patent: September 11, 2012Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Binhaku Taruishi, Hiroki Miyashita, Ken Shibata, Masashi Horiguchi
-
Patent number: 8223577Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.Type: GrantFiled: June 30, 2011Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Takesada Akiba, Shigeki Ueda, Toshikazu Tachibana, Masashi Horiguchi
-
Publication number: 20120161889Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.Type: ApplicationFiled: December 10, 2011Publication date: June 28, 2012Inventors: Osamu OZAWA, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
-
Publication number: 20120069692Abstract: A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing.Type: ApplicationFiled: September 21, 2011Publication date: March 22, 2012Inventors: BINHAKU TARUISHI, HIROKI MIYASHITA, KEN SHIBATA, MASASHI HORIGUCHI
-
Patent number: RE43222Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.Type: GrantFiled: June 24, 2010Date of Patent: March 6, 2012Assignee: Renesas Electronics CorporationInventors: Masashi Horiguchi, Mitsuru Hiraki
-
Patent number: RE44229Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.Type: GrantFiled: February 3, 2012Date of Patent: May 21, 2013Assignee: Renesas Electronics CorporationInventors: Masashi Horiguchi, Mitsuru Hiraki
-
Patent number: RE45118Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.Type: GrantFiled: May 21, 2013Date of Patent: September 9, 2014Assignee: Renesas Electronics CorporationInventors: Masashi Horiguchi, Mitsuru Hiraki