Abstract: A semiconductor device includes: a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down; and an internal voltage determining circuit for determining voltage of the internal power supply in which power is shut down. Voltage of the internal power supply in which power is shut down is generated from external power supply voltage by using a regulator circuit. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential. When power of the internal power supply is resumed, the regulator circuit is turned on, shorting is cancelled, increased voltage of the internal power supply is determined, operation of a circuit block is started, and the switch is turned on.

Abstract: A difference between both emitter voltages of a first transistor having an emitter through which a first current flows, and at least one second transistor having an emitter through which such a second current as to reach a current density thereof smaller than that of the emitter of the first transistor flows, is applied across a first resistor. A second resistor is provided between the emitter of the second transistor and a circuit's ground potential. A third resistor and a fourth resistor are respectively provided between collectors of the first and second transistors and a power supply voltage. Such an output voltage that a collector voltage of the first transistor and a collector voltage of the second transistor become equal is formed in response to the collector voltage of the first transistor and the collector voltage of the second transistor and supplied to bases of the first and second transistors in common.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low.

Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit block includes a first MOS transistor in which a leakage current flows even under a condition that a gate voltage is equal to a source voltage. Each of the first switching elements controls the leakage current flowing through a corresponding first MOS transistor of each circuit block. Also, while one of the first switching elements is controlled to reduce the leakage current flowing through the circuit block relating to one of the first switching elements, another one of the first switching elements is controlled to allow current to flow through the circuit block relating to another one of the first switching elements.

Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.

Abstract: A clock is located at a position close to a plurality of memory modules connected to a memory controller and located away from the controller, and wiring is carried out so that read access is preferential for transmission of read data. With respect to write data, a delay amount corresponding to a round-trip propagation delay time to each of the modules is measured and writing of the write data is carried out while maintaining a known time relationship between the clock and data. To measure round-trip reflection, lines are wired between the modules and a location detection circuit in a 1:1 relationship, and the circuit measures a time taken from a signal output time of a driver having the same impedance as that of the wired lines to a reflected-wave reception time of a hysteresis receiver.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.

Abstract: A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

Abstract: A difference between both emitter voltages of a first transistor having an emitter through which a first current flows, and at least one second transistor having an emitter through which such a second current as to reach a current density thereof smaller than that of the emitter of the first transistor flows, is applied across a first resistor. A second resistor is provided between the emitter of the second transistor and a circuit's ground potential. A third resistor and a fourth resistor are respectively provided between collectors of the first and second transistors and a power supply voltage. Such an output voltage that a collector voltage of the first transistor and a collector voltage of the second transistor become equal is formed in response to the collector voltage of the first transistor and the collector voltage of the second transistor and supplied to bases of the first and second transistors in common.

Abstract: A constant current is formed by supplying voltage differences between bases and emitters of a first transistor which allows a first current to flow in the emitter thereof and a second transistor which allows a second current having a current density larger than a current density of the first transistor to flow in an emitter thereof to a first resistance. A second resistance is provided on a ground potential side of a circuit in series with the first resistance. A third and a fourth resistances are provided between collectors and the power supply voltages of the first transistor and the second transistor. Both collector voltages of the first and second transistors are supplied to a differential amplifier circuit having the CMOS constitution thus forming an output voltage and, at the same time, the output voltage is supplied to bases of the first transistor and the second transistor in common.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: A difference between both emitter voltages of a first transistor having an emitter through which a first current flows, and at least one second transistor having an emitter through which such a second current as to reach a current density thereof smaller than that of the emitter of the first transistor flows, is applied across a first resistor. A second resistor is provided between the emitter of the second transistor and a circuit's ground potential. A third resistor and a fourth resistor are respectively provided between collectors of the first and second transistors and a power supply voltage. Such an output voltage that a collector voltage of the first transistor and a collector voltage of the second transistor become equal is formed in response to the collector voltage of the first transistor and the collector voltage of the second transistor and supplied to bases of the first and second transistors in common.

Abstract: With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.