Patents by Inventor Masataka Ikeda

Masataka Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152052
    Abstract: A substrate processing apparatus includes: a carrier block, into which a carrier storing a substrate is carried; a processing block including a liquid processing module that supplies a processing liquid to the substrate transferred from the carrier block, thereby performing a liquid processing; and an interface block, to which the substrate is transferred from the processing block. The interface block includes a liquid storage, in which a bottle storing the processing liquid is disposed. The carrier block includes a liquid feeder that feeds the processing liquid supplied from the liquid storage, to the liquid processing module. The liquid feeder includes a filter that filters the processing liquid supplied from the liquid storage, and a first pump that pumps the processing liquid toward the liquid processing module.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Inventors: Masataka TANAKA, Tsunaki IKEDA, Yuta NISHIYAMA
  • Patent number: 11968863
    Abstract: A display panel is provided. The display panel includes a display region, a functional layer, a first insulating film, and a first conductive film; the display region includes a pixel; the pixel includes a display element and a pixel circuit; the display element includes a first electrode and a second electrode; the second electrode includes a first opening portion; the functional layer includes the pixel circuit, a second opening portion, and an auxiliary wiring; the pixel circuit is electrically connected to the display element in the second opening portion; the auxiliary wiring includes a region overlapping with the first opening portion; the first insulating film includes a third opening portion; the third opening portion includes a region overlapping with the first opening portion; and the first conductive film is electrically connected to the second electrode and the auxiliary wiring in the third opening portion.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Masataka Nakada, Tomoya Aoyama
  • Publication number: 20230369348
    Abstract: A display device includes a first pixel, a second pixel, and a third pixel arranged in a first direction in a display area arranged on a first substrate, a first source wiring, a second wiring, and a third wiring extending in the first direction, and connected to each of the first pixel to the third pixel, and a first gate wiring, a second gate wiring, and a third wiring intersecting the first direction, and connected to each of the first pixel to the third pixel. The first pixel includes a first transistor electrically connected to the first gate wiring and the first source wiring and a liquid crystal element electrically connected to the first transistor, the first pixel to the third pixel are arranged between the first source wiring and the third source wiring, and the second source wiring, and the first source wiring intersects the third source wiring.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 16, 2023
    Applicant: Japan Display Inc.
    Inventors: Kentaro KAWAI, Masataka IKEDA, Hirotaka HAYASHI, Yuuji OOMORI, Yoshihide OHUE
  • Publication number: 20230352502
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 2, 2023
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
  • Publication number: 20230315914
    Abstract: An authentication device includes a display device and a control circuit. The display device includes a first transistor having a gate and a source electrode, a photoelectric conversion element having a first electrode connected to a drain electrode of the first transistor, and a capacitive element connected between the gate electrode and the drain electrode. The control circuit controls resetting the drain electrode, initializing the gate electrode, storing first charge corresponding to the threshold of the first transistor in the capacitive element, setting the threshold of the first transistor, transmitting a signal including data for causing the photoelectric conversion element to emit to the gate electrode, adding second charge corresponding data to the first charge, causing the photoelectric conversion element to emit, reading a voltage corresponding to the first charge and the second charge, and generating a PUF-ID using the voltage.
    Type: Application
    Filed: March 10, 2023
    Publication date: October 5, 2023
    Applicant: Japan Display Inc.
    Inventor: Masataka IKEDA
  • Publication number: 20230251545
    Abstract: According to one embodiment, a display device includes a first substrate including a plurality of pixel electrodes that include a plurality of first pixel electrodes and a plurality of second pixels, and an inorganic insulating layer that covers the plurality of pixel electrodes, a second substrate including a counter-substrate opposed to the plurality of pixel electrodes, and an electrophoretic layer arranged between the first substrate and the second substrate.
    Type: Application
    Filed: February 9, 2023
    Publication date: August 10, 2023
    Applicant: Japan Display Inc.
    Inventor: Masataka IKEDA
  • Patent number: 11710751
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 25, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma, Masataka Ikeda, Takeshi Aoki
  • Publication number: 20230215957
    Abstract: According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.
    Type: Application
    Filed: March 10, 2023
    Publication date: July 6, 2023
    Applicant: Japan Display Inc.
    Inventors: Masataka IKEDA, Hirotaka HAYASHI, Hitoshi TANAKA
  • Patent number: 11694454
    Abstract: An information processing device comprises an electronic device, an averaging circuit acquiring output signals from the electronic device multiple times in a predetermined period and averaging the signals acquired multiple times, a memory circuit storing an averaged signal averaged by the averaging circuit and a PUF-ID extraction circuit generating a unique identifier based on the averaged signal.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: July 4, 2023
    Assignee: Japan Display Inc.
    Inventor: Masataka Ikeda
  • Publication number: 20230208658
    Abstract: A detection device includes a pixel including a photodiode connected to a gate electrode of a first transistor, and a control circuit configured to control an operation of the pixel in a reset period (including a first and a second periods) for resetting the gate electrode, an exposure period for exposing the photo diode, and a read-out period (a fourth period) to read out a voltage associated with the exposure of the photodiode. The control circuit is configured to read out a first voltage during the first period, read out a second voltage during the second period after stopping a supply of a reset voltage to the gate electrode, read out a third voltage in the fourth period after the exposure period, output a difference value between the first and the second voltages as PUF-ID data and a difference value between the third and the second voltages as detection data.
    Type: Application
    Filed: March 1, 2023
    Publication date: June 29, 2023
    Applicant: Japan Display Inc.
    Inventor: Masataka IKEDA
  • Patent number: 11682732
    Abstract: According to one embodiment, a semiconductor layer includes a base, a scanning line disposed over the base, a signal line disposed over the base, a transistor overlapping the scanning line and the signal line and including a first oxide semiconductor layer connected to the signal line, and second oxide semiconductor layers disposed in a same layer as the first oxide semiconductor layer. The second oxide semiconductor layers are disposed around the transistor, and the second oxide semiconductor layers are floating.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: June 20, 2023
    Assignee: Japan Display Inc.
    Inventors: Hirotaka Hayashi, Masataka Ikeda
  • Patent number: 11626520
    Abstract: According to one embodiment, a semiconductor substrate includes a first basement, a gate line, a source line, an insulating film, a first pixel electrode, and a first transistor and a second transistor connected parallel at positions between the source line and the first pixel electrode. Each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor includes a first region, a second region, and a channel region. The first semiconductor layer and the second semiconductor layer are in contact with a first surface that is a surface of the insulating film on the source line side. The channel region of each of the first semiconductor layer and the second semiconductor layer wholly overlaps the gate line.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 11, 2023
    Assignee: JAPAN DISPLAY INC.
    Inventors: Masataka Ikeda, Hirotaka Hayashi, Hitoshi Tanaka
  • Patent number: 11580919
    Abstract: The display device includes at least one pixel having a first capacitive element having a first terminal and a transistor connected to the first terminal and having a second terminal and a gate electrode. A driving method of the display device including in a first frame, a signal with a first pulse width is supplied to the gate electrode of the transistor, and a first voltage is written from the second terminal to the first terminal. In the second frame after the first frame, a signal with a second pulse width is supplied to the gate electrode, and the first terminal holds the first voltage. In the third frame after the second frame, a signal with a third pulse width is supplied to the gate electrode, and the second voltage is written from the second terminal to the first terminal.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: February 14, 2023
    Assignee: Japan Display Inc.
    Inventor: Masataka Ikeda
  • Publication number: 20220317790
    Abstract: A touch panel capable of performing display and sensing along a curved surface or a touch panel that maintains high detection sensitivity even when it is curved along a curved surface is provided. A flexible display panel is placed along a curved portion included in a surface of a support. A first film layer is attached along a surface of the display panel by a bonding layer. Second to n-th film layers (n is an integer of 2 or more) are sequentially attached along a surface of the first film layer by bonding layers. A flexible touch sensor is attached along a surface of the n-th film layer by a bonding layer.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Daiki NAKAMURA, Masataka IKEDA
  • Publication number: 20220319447
    Abstract: The display device includes at least one pixel having a first capacitive element having a first terminal and a transistor connected to the first terminal and having a second terminal and a gate electrode. A driving method of the display device including in a first frame, a signal with a first pulse width is supplied to the gate electrode of the transistor, and a first voltage is written from the second terminal to the first terminal. In the second frame after the first frame, a signal with a second pulse width is supplied to the gate electrode, and the first terminal holds the first voltage. In the third frame after the second frame, a signal with a third pulse width is supplied to the gate electrode, and the second voltage is written from the second terminal to the first terminal.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 6, 2022
    Applicant: Japan Display Inc.
    Inventor: Masataka IKEDA
  • Publication number: 20220273709
    Abstract: The present invention provides a pharmaceutical for preventing and/or treating non-ischemic cardiomyopathy, the pharmaceutical comprising dendritic cells obtained by a method comprising a step of culturing mononuclear cells in the presence of GM-CSF and IL-2 and a step of pulsing the cultured cells with ?-galactosylceramide.
    Type: Application
    Filed: July 10, 2020
    Publication date: September 1, 2022
    Applicant: KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATION
    Inventors: Hiroyuki TSUTSUI, Tomomi IDE, Kisho OHTANI, Shoji MATSUSHIMA, Masataka IKEDA
  • Patent number: 11327374
    Abstract: A display device includes a first direction, a plurality of pixels arranged in a second direction intersecting the first direction, at least one scanning signal line connected to the plurality of pixels, a scanning signal line driving circuit connected to the scanning line, the scanning signal line driving circuit includes a switch for outputting a signal to the scanning signal line, a first power supply line for providing a first voltage to the switch, a second power supply line for providing a second voltage smaller than the first voltage to the switch, and the switch is provided between the first power supply line and the second power supply line, a line width of the second power supply line is 4 times the line width of the first power supply line or more and 40 times the line width of the first power supply line or less.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: May 10, 2022
    Assignee: Japan Display Inc.
    Inventors: Masataka Ikeda, Gen Koide
  • Publication number: 20220020793
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 20, 2022
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
  • Publication number: 20220004757
    Abstract: An information processing device comprises an electronic device, an averaging circuit acquiring output signals from the electronic device multiple times in a predetermined period and averaging the signals acquired multiple times, a memory circuit storing an averaged signal averaged by the averaging circuit and a PUF-ID extraction circuit generating a unique identifier based on the averaged signal.
    Type: Application
    Filed: September 22, 2021
    Publication date: January 6, 2022
    Applicant: Japan Display Inc.
    Inventor: Masataka IKEDA
  • Patent number: 11194206
    Abstract: According to one embodiment, a semiconductor substrate includes a signal line including a first area overlapping a first concave groove portion and a second area not overlapping the first concave groove portion. The signal line includes a first layer and a second layer. A first end portion of the first layer of the first area projects from a side surface of the second layer in a direction parallel to a plane of the first base. The first layer of the first area includes a first portion between the side surface of the second layer and the first end portion. The first portion is in contact with a side surface of the first concave groove portion, and the side surface of the second layer is covered with the first portion in the first concave groove portion.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: December 7, 2021
    Assignee: JAPAN DISPLAY INC.
    Inventors: Gen Koide, Masataka Ikeda