Patents by Inventor Masataka Kano

Masataka Kano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9837036
    Abstract: A gate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: December 5, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tadashi Amino, Jong Hee Kim, Masataka Kano, Jun Hyun Park
  • Patent number: 9601518
    Abstract: A thin film transistor display panel including: a first insulating substrate; a first semiconductor disposed between the first insulating substrate and a first gate insulating layer; a gate electrode disposed on the first gate insulating layer, the gate electrode overlapping the first semiconductor; a second gate insulating layer disposed on the gate electrode; a second semiconductor disposed on the second gate insulating layer, the second semiconductor overlapping the gate electrode; an interlayer insulating layer disposed on the second semiconductor; and a source electrode and a drain electrode disposed on the interlayer insulating layer spaced apart from each other, the source electrode and the drain electrode connected to the first semiconductor and the second semiconductor.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: March 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeon Keon Moon, Masataka Kano, So Young Koo, Myoung Hwa Kim, Jun Hyung Lim
  • Publication number: 20170052417
    Abstract: Provided is a display device. The display device includes: a substrate; a light blocking pattern disposed on the substrate; a semiconductor pattern disposed on the light blocking pattern; a gate insulating layer disposed on the semiconductor pattern; a gate wiring; an interlayer insulating layer formed on the gate wiring; a first contact hole for exposing the source area; a data wiring disposed to extend in the second direction on the interlayer insulating layer and electrically connected to the source area via the first contact hole; a first passivation layer disposed on the data wiring; a second contact hole, which is disposed between the neighboring protrusion portions of the light blocking pattern so as not to overlap the light blocking pattern, and exposes the drain area; and a pixel electrode disposed on the first passivation layer and electrically connected to the drain area through the second contact hole.
    Type: Application
    Filed: March 8, 2016
    Publication date: February 23, 2017
    Inventors: Jung Hun NOH, Masataka KANO, Yeon Keon MOON, Keun Kyu SONG, Jun Ho SONG, Hyun Sup LEE, Sang Hee JANG, Byung Seok CHOI
  • Patent number: 9543336
    Abstract: A thin-film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a first self-assembled monolayer disposed on the first gate electrode, a gate insulating layer disposed on the first self-assembled monolayer, a semiconductor disposed on the gate insulating layer, a drain electrode overlapping the semiconductor, the drain electrode being separated from and facing a source electrode with respect to the semiconductor, a first interlayer insulating layer disposed on the source electrode and the drain electrode, a second self-assembled monolayer disposed on the first interlayer insulating layer, a second gate electrode disposed on the second self-assembled monolayer, a second interlayer insulating layer disposed on the second gate electrode, and a pixel electrode disposed on the second interlayer insulating layer and connected to the drain electrode.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 10, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Masataka Kano, Ji Hun Lim, Yeon Keon Moon, Jun Hyung Lim, So Young Koo, Myoung Hwa Kim
  • Publication number: 20160365368
    Abstract: A thin-film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a first self-assembled monolayer disposed on the first gate electrode, a gate insulating layer disposed on the first self-assembled monolayer, a semiconductor disposed on the gate insulating layer, a drain electrode overlapping the semiconductor, the drain electrode being separated from and facing a source electrode with respect to the semiconductor, a first interlayer insulating layer disposed on the source electrode and the drain electrode, a second self-assembled monolayer disposed on the first interlayer insulating layer, a second gate electrode disposed on the second self-assembled monolayer, a second interlayer insulating layer disposed on the second gate electrode, and a pixel electrode disposed on the second interlayer insulating layer and connected to the drain electrode.
    Type: Application
    Filed: December 9, 2015
    Publication date: December 15, 2016
    Inventors: Masataka KANO, Ji Hun LIM, Yeon Keon MOON, Jun Hyung LIM, So Young KOO, Myoung Hwa KIM
  • Patent number: 9478667
    Abstract: A thin film transistor substrate includes a substrate, a bottom gate on the substrate, a first insulating layer on the substrate and on the bottom gate, a drain on the first insulating layer, a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain, an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source, a second insulating layer on the drain, the source, and the active layer, and a top gate on the second insulating layer.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: October 25, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yeon Keon Moon, Masataka Kano, Sung-Hoon Yang, Ji Hun Lim, So Young Koo, Myoung Hwa Kim, Jun Hyung Lim
  • Publication number: 20160300526
    Abstract: A display device includes: a plurality of pixels, wherein each of the plurality of pixels includes at least two double-gate transistors including a first gate electrode and a second gate electrode; conduction between source electrodes and drain electrodes of the at least two double-gate transistors is controlled by a voltage applied to the first gate electrode, and electrical connection between the second gate electrode and the first gate electrode of each of the at least two double-gate transistors is determined depending on a polarity of a voltage applied on average to each of the at least two double-gate transistors.
    Type: Application
    Filed: October 29, 2015
    Publication date: October 13, 2016
    Inventors: Ji Hun Lim, Yeon Keon Moon, Masataka Kano, Jun Hyung Lim
  • Publication number: 20160300859
    Abstract: A thin film transistor display panel including: a first insulating substrate; a first semiconductor disposed between the first insulating substrate and a first gate insulating layer; a gate electrode disposed on the first gate insulating layer, the gate electrode overlapping the first semiconductor; a second gate insulating layer disposed on the gate electrode; a second semiconductor disposed on the second gate insulating layer, the second semiconductor overlapping the gate electrode; an interlayer insulating layer disposed on the second semiconductor; and a source electrode and a drain electrode disposed on the interlayer insulating layer spaced apart from each other, the source electrode and the drain electrode connected to the first semiconductor and the second semiconductor.
    Type: Application
    Filed: September 16, 2015
    Publication date: October 13, 2016
    Inventors: Yeon Keon MOON, Masataka KANO, So Young KOO, Myoung Hwa KIM, Jun Hyung LIM
  • Patent number: 9412771
    Abstract: A method of manufacturing a thin film transistor and a method of manufacturing a display substrate having the same are disclosed. In one aspect, the method of manufacturing a thin film transistor comprises forming an oxide semiconductor layer over a substrate, plasma-treating the oxide semiconductor layer with a plasma generated from a nitrogen gas or a nitric oxide gas so as to decrease defects in the oxide semiconductor layer, and annealing the plasma-treated oxide semiconductor layer to form a channel layer.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: August 9, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soyoung Koo, Myounghwa Kim, Sangho Park, Jun Hyung Lim, Masataka Kano
  • Publication number: 20160210926
    Abstract: A Rate driving circuit including: a plurality of stages outputting signals to gate lines, the stages includes a first transistor of which one end and a control terminal are connected, one end and the control terminal are connected with a first input terminal, and the other end is connected to a second node, a second transistor including a control terminal connected to a first node, connected with a clock input terminal, and the other end connected to a first output terminal, a first capacitor of which one end is connected to the first node, the other end is connected to the other end of the second transistor and the first output terminal, and a third transistor of which one end is connected to the other end of the first transistor, the other end is connected with the first node, and a control terminal is connected to a third node.
    Type: Application
    Filed: September 23, 2015
    Publication date: July 21, 2016
    Inventors: Tadashi AMINO, Jong Hee KIM, Masataka KANO, Jun Hyun PARK
  • Publication number: 20160155753
    Abstract: The display device includes a substrate, a first gate line extending in a first direction on the substrate, a gate insulating layer formed on the substrate to cover the first gate line, a first semiconductor pattern formed on the gate insulating layer to overlap the first gate line, and including a first region and a second region, a first data line extending in a second direction that is crossing the first gate line on the gate insulating layer, and including a source electrode region that overlaps the first region of the first semiconductor pattern, a drain electrode spaced apart from the source electrode region and formed on the second region of the first semiconductor pattern, and a pixel electrode formed on the drain electrode and electrically connected to the drain electrode. The first semiconductor pattern is arranged in a third direction between the first direction and the second direction.
    Type: Application
    Filed: March 20, 2015
    Publication date: June 2, 2016
    Inventors: MASATAKA KANO, Yeon Keon MOON, Jung Hun NOH, Jun Hyung LIM, So Young KOO, Myoung Hwa KIM
  • Publication number: 20160133754
    Abstract: A thin film transistor substrate includes a substrate, a bottom gate on the substrate, a first insulating layer on the substrate and on the bottom gate, a drain on the first insulating layer, a source on the first insulating layer, the source including a first source at a first side of the drain and a second source at a second side of the drain, an active layer on the first insulating layer, the active layer including a first active layer contacting the drain and the first source and a second active layer contacting the drain and the second source, a second insulating layer on the drain, the source, and the active layer, and a top gate on the second insulating layer.
    Type: Application
    Filed: March 18, 2015
    Publication date: May 12, 2016
    Inventors: Yeon Keon MOON, Masataka KANO, Sung-Hoon YANG, Ji Hun LIM, So Young KOO, Myoung Hwa KIM, Jun Hyung LIM
  • Publication number: 20160013257
    Abstract: A method of manufacturing a thin film transistor and a method of manufacturing a display substrate having the same are disclosed. In one aspect, the method of manufacturing a thin film transistor comprises forming an oxide semiconductor layer over a substrate, plasma-treating the oxide semiconductor layer with a plasma generated from a nitrogen gas or a nitric oxide gas so as to decrease defects in the oxide semiconductor layer, and annealing the plasma-treated oxide semiconductor layer to form a channel layer.
    Type: Application
    Filed: July 8, 2015
    Publication date: January 14, 2016
    Inventors: SOYOUNG KOO, Myounghwa Kim, Sangho Park, Jun Hyung Lim, Masataka Kano
  • Publication number: 20150144941
    Abstract: Disclosed is a display substrate including a driving unit on a substrate comprising a first thin film transistor and a display unit on the substrate being adjacent to the driving unit and comprising a second thin film transistor.
    Type: Application
    Filed: October 10, 2014
    Publication date: May 28, 2015
    Inventors: Masataka KANO, Sang-Ho PARK, So-Young KOO, Myoung-Hwa KIM, Yeon-Hong KIM, Jung-Hun NOH, Jun-Hyung LIM, Sang-Hee JANG
  • Patent number: 8920677
    Abstract: A scintillator material is made of a zinc-oxide single crystal grown on a +C surface or a ?C surface of a plate-shaped seed crystal of zinc oxide including a C surface as a main surface. The zinc-oxide single crystal contains In and Li. In response to an incident radiation, the scintillator material emits fluorescence of less than 20-ps fluorescence lifetime.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: December 30, 2014
    Assignee: Daishinku Corporation
    Inventors: Masataka Kano, Akira Wakamiya, Kohei Yamanoi, Toshihiko Shimizu, Nobuhiko Sarukura, Dirk Ehrentraut, Tsuguo Fukuda
  • Patent number: 8877551
    Abstract: In a method of manufacturing a thin film transistor, a gate electrode is formed on a first surface of a base substrate, a oxide semiconductor layer, insulation layer and photo resist layer are formed an the fast surface of the base substrate having the gate electrode. The insulation layer and the oxide semiconductor layer are patterned using a first photo resist pattern to form an etch-stopper and an active pattern. A source and a drain electrode are formed on the base substrate having the active pattern and the etch-stopper, the source electrode and the drain electrode are overlapped with both ends of the etch-stopper and spaced apart from each other. Therefore, a manufacturing cost may be decreased by omitting a mask when forming the active pattern and the etch-stopper.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 4, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Bo-Sung Kim, Jun-Ho Song, Doo-Na Kim, Kang-Moon Jo, Tae-Young Choi, Masataka Kano, Yeon-Taek Jeong
  • Patent number: 8785921
    Abstract: A device capable of having an easy production process and achieving a long lifetime. The device has a substrate, two or more electrodes facing each other disposed on the substrate and a positive hole injection transport layer disposed between two electrodes among the two or more electrodes. The positive hole injection transport layer has a transition metal-containing nanoparticle containing at least a transition metal compound including a transition metal oxide, a transition metal and a protecting agent, or at least the transition metal compound including the transition metal oxide, and the protecting agent.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: July 22, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Shigehiro Ueno, Keisuke Hashimoto, Masato Okada, Seiji Take, Yosuke Taguchi, Masataka Kano, Shin-ya Fujimoto
  • Patent number: 8778233
    Abstract: The present invention is to provide a device capable of having an easy production process and achieving a long lifetime. A device comprising a substrate, two or more electrodes facing each other disposed on the substrate and a positive hole injection transport layer disposed between two electrodes among the two or more electrodes, wherein the positive hole injection transport layer comprises a transition metal-containing nanoparticle containing at least a transition metal compound including a transition metal oxide, a transition metal and a protecting agent, or at least the transition metal compound including the transition metal oxide, and the protecting agent.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: July 15, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Shigehiro Ueno, Keisuke Hashimoto, Masato Okada, Seiji Take, Yosuke Taguchi, Masataka Kano, Shin-ya Fujimoto
  • Patent number: 8673185
    Abstract: The present invention is to provide a device capable of having an easy production process and achieving a long lifetime. A device comprising a substrate, two or more electrodes facing each other disposed on the substrate and a positive hole injection transport layer disposed between two electrodes among the two or more electrodes, wherein the positive hole injection transport layer comprises a transition metal-containing nanoparticle containing at least a transition metal compound including a transition metal oxide, a transition metal and a protecting agent, or at least the transition metal compound including the transition metal oxide, and the protecting agent.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: March 18, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Shigehiro Ueno, Keisuke Hashimoto, Masato Okada, Seiji Take, Yosuke Taguchi, Masataka Kano, Shin-ya Fujimoto
  • Publication number: 20130234169
    Abstract: In a method of manufacturing a thin film transistor, a gate electrode is formed on a first surface of a base substrate, a oxide semiconductor layer, insulation layer and photo resist layer are formed an the fast surface of the base substrate having the gate electrode. The insulation layer and the oxide semiconductor layer are patterned using a first photo resist pattern to form an etch-stopper and an active pattern. A source and a drain electrode are formed on the base substrate having the active pattern and the etch-stopper, the source electrode and the drain electrode are overlapped with both ends of the etch-stopper and spaced apart from each other. Therefore, a manufacturing cost may be decreased by omitting a mask when forming the active pattern and the etch-stopper.
    Type: Application
    Filed: September 14, 2012
    Publication date: September 12, 2013
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Bo-Sung KIM, Jun-Ho SONG, Doo-Na KIM, Kang-Moon JO, Tae-Young CHOI, Masataka KANO, Yeon-Taek JEONG