Abstract: A control device according to the present invention includes a plurality of arithmetic units that operate in parallel. A sensor value of the control amount is input to the first arithmetic unit in a signal transmission sequence, and a correction amount for the manipulation amount is output from the last arithmetic unit in the signal transmission sequence. The first arithmetic unit has a controller that produces an output by processing the input sensor value, and the arithmetic units other than the first arithmetic unit has a delay element that delays an input by a predetermined number of steps and a controller that produces an output by processing the delayed input.

Abstract: The present invention relates to a control device design method for a control device that determines a manipulation amount of a control object having a dead time by feedback control so as to bring a control amount of the control object closer to a target value. The method according to the present invention includes a step of designing a feedback loop that computes a correction amount for the manipulation amount using a plurality of controllers including a prediction model of the control object, a step of deriving the same number of delay elements as the plurality of controllers from a dead time element of the prediction model, and a step of allocating the plurality of controllers associated with the delay elements to a plurality of arithmetic units so that the computation of the feedback loop is performed by parallel computation by the plurality of arithmetic units that operate in parallel.

Abstract: The present invention relates to a control device design method for a control device that determines a manipulation amount of a control object having a dead time by feedback control so as to bring a control amount of the control object closer to a target value. The method according to the present invention includes a step of designing a feedback loop that computes a correction amount for the manipulation amount using a plurality of controllers including a prediction model of the control object, a step of deriving the same number of delay elements as the plurality of controllers from a dead time element of the prediction model, and a step of allocating the plurality of controllers associated with the delay elements to a plurality of arithmetic units so that the computation of the feedback loop is performed by parallel computation by the plurality of arithmetic units that operate in parallel.

Abstract: A control device according to the present invention includes a plurality of arithmetic units that operate in parallel. A sensor value of the control amount is input to the first arithmetic unit in a signal transmission sequence, and a correction amount for the manipulation amount is output from the last arithmetic unit in the signal transmission sequence. The first arithmetic unit has a controller that produces an output by processing the input sensor value, and the arithmetic units other than the first arithmetic unit has a delay element that delays an input by a predetermined number of steps and a controller that produces an output by processing the delayed input.

Abstract: The present invention relates to a control device design method for a control device that determines a manipulation amount of a control object having a dead time by feedback control so as to bring a control amount of the control object closer to a target value. The method according to the present invention includes a step of designing a feedback loop that computes a correction amount for the manipulation amount using a plurality of controllers including a prediction model of the control object, a step of deriving the same number of delay elements as the plurality of controllers from a dead time element of the prediction model, and a step of allocating the plurality of controllers associated with the delay elements to a plurality of arithmetic units so that the computation of the feedback loop is performed by parallel computation by the plurality of arithmetic units that operate in parallel.

Abstract: For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20a through 20n from each other.

Abstract: Disclosed is an automatic optimization system capable of searching for an allocation with a good performance from among a plurality of task allocations which can be scheduled in a system of a development target configured with a plurality of periodic tasks. A task allocation optimization system for a multi-core processor including a plurality of cores calculates a response time of each of a plurality of tasks which are core allocation decision targets, and outputs an accumulative value of the calculated response time as an evaluation function value which is an index representing excellence of a task allocation. A task allocation from which a good evaluation function value is calculated is searched based on the evaluation function value. A candidate having a good evaluation function value among a plurality of searched task allocation candidates is held.

Abstract: Provided is the information communication processing device capable of executing terminal function switching control in linkage with an external communication content on one information communication processing device based on the external communication content without a problem in switching. The information communication processing device has at least one information processing device having a plurality of function environments for executing an application, and a switching control unit for switching a function environment, in which the switching control unit determines a function environment to be switched based on contents of communication with the outside of the information communication processing device and sets context of the function environment to be switched at context of a function environment being executed, thereby executing switching to the function environment to be switched.

Abstract: A device and a method are provided for increasing processing speed and for ensuring system security when an application or a driver is added. The device includes a first CPU group that executes software composed of basic processing and an OS; a second CPU group that executes software composed of additional processing and OS corresponding to the additional processing, inter-processor communication means used for communication between the first CPU and the second CPU, and access control means that controls access made by the second CPU to a memory and/or an input/output device.

Abstract: A parallel sorting apparatus is provided whose sorting processing is speeded up. A reference value calculation section calculates a plurality of reference values serving as boundaries of intervals used for allocating input data depending on the magnitude of a value. An input data aggregation section partitions the input data into a plurality of input data regions, and calculates, by parallel processing, mapping information used for allocating data in each of the partitioned input data regions to the plurality of intervals that have boundaries on the reference values calculated by the reference value calculation section. A data allocation section allocates, by parallel processing, data in each of the input data regions to the plurality of intervals in accordance with the mapping information calculated by the input data aggregation section. An interval sorting section individually sorts, by parallel processing, data in the plurality of intervals allocated by the data allocation section.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

Abstract: Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory. The information processing device comprises a basic side CPU 100 for executing basic processing and an addition side CPU 200 for executing additional processing, in which a transfer management unit 300 provided on the basic side CPU 100 transfers execution environment data 1000 including constitution information of an execution environment 30 of the additional processing to be executed on the addition side CPU and data in a memory corresponding to the execution environment to other information processing device and restores the execution environment to re-start the addition side CPU based on the received execution environment data 1000.

Abstract: On a parallel processing system by an OS for single processors which operates, on a multiprocessor, an OS for single processors and an existing application to realize parallel processing by the multiprocessor with respect to the application, each processor includes a communication proxy unit which transfers data between tasks spreading over the processors by proxy and the communication proxy unit on a processor in which a task on a transmission side operates holds information about an address, on a processor, of a task on a reception side to receive data transferred from the task on the transmission side as proxy for the task on the reception side.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

Abstract: The information processing device which recovers a domain developing a fault caused by added application and device driver while maintaining security and reliability includes a plurality of processors, wherein the plurality of processors form a plurality of domains according to processing contents to be executed, and the processors in different domains communicate with each other through a communication unit, and which further includes a recovery unit for executing, for a domain developing a fault, failure recovery processing based on a failure recovery request notified by the domain and a recovery condition set in advance for each domain.

Abstract: Disclosed is an automatic optimization system capable of searching for an allocation with a good performance from among a plurality of task allocations which can be scheduled in a system of a development target configured with a plurality of periodic tasks. A task allocation optimization system for a multi-core processor including a plurality of cores calculates a response time of each of a plurality of tasks which are core allocation decision targets, and outputs an accumulative value of the calculated response time as an evaluation function value which is an index representing excellence of a task allocation. A task allocation from which a good evaluation function value is calculated is searched based on the evaluation function value. A candidate having a good evaluation function value among a plurality of searched task allocation candidates is held.

Abstract: Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory. The information processing device comprises a basic side CPU 100 for executing basic processing and an addition side CPU 200 for executing additional processing, in which a transfer management unit 300 provided on the basic side CPU 100 transfers execution environment data 1000 including constitution information of an execution environment 30 of the additional processing to be executed on the addition side CPU and data in a memory corresponding to the execution environment to other information processing device and restores the execution environment to re-start the addition side CPU based on the received execution environment data 1000.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. Transmission side adaptors store first delivery information, and control delivery of the request signal to be received from the first core in accordance with the first delivery information. Reception side adaptors store second delivery information, and control delivery of the request signal to be received through the interconnecting network to the second core in accordance with the second delivery information. The first delivery information and the second delivery information are hierarchically set.

Abstract: A semiconductor integrated circuit of the invention comprises a plurality of cores, and an interconnecting network including adaptors connected to each of the cores and a plurality of routers connecting the adaptors to communicate therebetween. The adaptors keep delivery information indicating a delivery condition of a request signal received from the cores and control delivery of the request signal received from the cores in accordance with the delivery information.

Abstract: For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20aA through 20n from each other.