Patents by Inventor Masato Edahiro

Masato Edahiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100031008
    Abstract: A parallel sorting apparatus is provided whose sorting processing is speeded up. A reference value calculation section calculates a plurality of reference values serving as boundaries of intervals used for allocating input data depending on the magnitude of a value. An input data aggregation section partitions the input data into a plurality of input data regions, and calculates, by parallel processing, mapping information used for allocating data in each of the partitioned input data regions to the plurality of intervals that have boundaries on the reference values calculated by the reference value calculation section. A data allocation section allocates, by parallel processing, data in each of the input data regions to the plurality of intervals in accordance with the mapping information calculated by the input data aggregation section. An interval sorting section individually sorts, by parallel processing, data in the plurality of intervals allocated by the data allocation section.
    Type: Application
    Filed: December 4, 2007
    Publication date: February 4, 2010
    Inventors: Masato Edahiro, Yoshiko Yamashita
  • Publication number: 20090247142
    Abstract: Provided is the information communication processing device capable of executing terminal function switching control in linkage with an external communication content on one information communication processing device based on the external communication content without a problem in switching. The information communication processing device has at least one information processing device having a plurality of function environments for executing an application, and a switching control unit for switching a function environment, in which the switching control unit determines a function environment to be switched based on contents of communication with the outside of the information communication processing device and sets context of the function environment to be switched at context of a function environment being executed, thereby executing switching to the function environment to be switched.
    Type: Application
    Filed: July 18, 2007
    Publication date: October 1, 2009
    Inventors: Hiroaki Inoue, Masato Edahiro
  • Publication number: 20090119541
    Abstract: The information processing device which recovers a domain developing a fault caused by added application and device driver while maintaining security and reliability includes a plurality of processors, wherein the plurality of processors form a plurality of domains according to processing contents to be executed, and the processors in different domains communicate with each other through a communication unit, and which further includes a recovery unit for executing, for a domain developing a fault, failure recovery processing based on a failure recovery request notified by the domain and a recovery condition set in advance for each domain.
    Type: Application
    Filed: February 23, 2006
    Publication date: May 7, 2009
    Applicant: NEC CORPORATION
    Inventors: Hiroaki Inoue, Junji Sakai, Tsuyoshi Abe, Masaki Uekubo, Noriaki Suzuki, Masato Edahiro
  • Patent number: 7526673
    Abstract: In a parallel processing system by an OS for single processors which operates an OS for single processors and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, with the multiprocessor being logically divided into two groups of a first processor side and a second processor side, a unit of work that can be parallelized within the application operating on a processor on the first processor side is controlled as a new unit of work on a processor on the second processor side.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: April 28, 2009
    Assignee: NEC Corporation
    Inventors: Hiroaki Inoue, Yoshiyuki Ito, Junji Sakai, Masato Edahiro
  • Patent number: 7516323
    Abstract: On a parallel processing system which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, an OS service unit which provides services of the OS for single processors to a unit of work which can be parallelized within the application controls security function with respect to a processing request from the unit of work in response to the processing request.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: April 7, 2009
    Assignee: NEC Corporation
    Inventors: Hiroaki Inoue, Yoshiyuki Ito, Junji Sakai, Masato Edahiro
  • Patent number: 7464377
    Abstract: In the application parallel processing system, on specific one of processors forming a multi-processor, an application is operated independently of other processors and on other processors, a function expansion module is operated in parallel processing under control of the application. As a result, even in such a data processing device internally provided with a processor whose processing capacity is small as a portable terminal, applications can be operated smoothly.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: December 9, 2008
    Assignee: NEC Corporation
    Inventors: Masato Edahiro, Junji Sakai, Tetsuya Minakami, Yoshiyuki Ito, Hiroaki Inoue
  • Publication number: 20080256550
    Abstract: The present invention relates to a parallel processing system by an OS for single processor capable of operating an OS for single processor and an existing application on a multiprocessor and achieving parallel processing by a multiprocessor with respect to the application, wherein the multiprocessor are logically divided into two groups, i.e., a first processor side and a second processor side, and units of work that are parallelizable within the application operating on the processors on the first processor side are controlled as new units of work on the processors on the second processor side.
    Type: Application
    Filed: June 16, 2008
    Publication date: October 16, 2008
    Inventors: Masato Edahiro, Yoshiyuki Ito, Junji Sakai, Tetsuya Minakami, Hiroaki Inoue
  • Patent number: 7418703
    Abstract: The present invention relates to a parallel processing system by an OS for single processor capable of operating an OS for single processor and an existing application on a multiprocessor and achieving parallel processing by a multiprocessor with respect to the application, wherein the multiprocessor are logically divided into two groups, i.e., a first processor side and a second processor side, and units of work that are parallelizable within the application operating on the processors on the first processor side are controlled as new units of work on the processors on the second processor side.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: August 26, 2008
    Assignee: NEC Corporation
    Inventors: Masato Edahiro, Yoshiyuki Ito, Junji Sakai, Tetsuya Minakami, Hiroaki Inoue
  • Publication number: 20080172667
    Abstract: In a parallel processing system by an OS for single processors which operates an OS for single processors and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, with the multiprocessor being logically divided into two groups of a first processor side and a second processor side, a unit of work that can be parallelized within the application operating on a processor on the first processor side is controlled as a new unit of work on a processor on the second processor side.
    Type: Application
    Filed: March 24, 2004
    Publication date: July 17, 2008
    Inventors: Hiroaki Inoue, Yoshiyuki Ito, Junji Sakai, Masato Edahiro
  • Patent number: 7325148
    Abstract: In a parallel processing system by an OS for single processors which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, a processor on a first processor side receives a request for activating or stopping a processor from a unit of work on any of the processors and controls a power supply management device of the OS for single processors to conduct activation or stop of the requested processor, while the processor requested to be activated or stop executes processing necessary for the activation or stop based on a notification from the first processor side.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: January 29, 2008
    Assignee: NEC Corporation
    Inventors: Hiroaki Inoue, Yoshiyuki Ito, Junji Sakai, Masato Edahiro
  • Publication number: 20080005794
    Abstract: A device and a method are provided for increasing processing speed and for ensuring system security when an application or a driver is added. The device includes a first CPU group 10A that executes software 20A composed of basic processing 22 and an OS 21A; a second CPU group 10B that executes software 20B composed of additional processing 23 and OS 21B corresponding to the additional processing, inter-processor communication means 40, and 402 used for communication between the first CPU 10A and the second CPU 10B, and access control means 30 that controls access made by the second CPU 10B to a memory 50 and/or an input/output device 60.
    Type: Application
    Filed: August 15, 2005
    Publication date: January 3, 2008
    Inventors: Hiroaki Inoue, Junji Sakai, Tsuyoshi Abe, Masato Edahiro
  • Publication number: 20050229184
    Abstract: On a parallel processing system by an OS for single processors which operates, on a multiprocessor, an OS for single processors and an existing application to realize parallel processing by the multiprocessor with respect to the application, each processor includes a communication proxy unit which transfers data between tasks spreading over the processors by proxy and the communication proxy unit on a processor in which a task on a transmission side operates holds information about an address, on a processor, of a task on a reception side to receive data transferred from the task on the transmission side as proxy for the task on the reception side.
    Type: Application
    Filed: March 16, 2005
    Publication date: October 13, 2005
    Inventors: Hiroaki Inoue, Junji Sakai, Tsuyoshi Abe, Masato Edahiro
  • Publication number: 20050015625
    Abstract: On a parallel processing system which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, an OS service unit which provides services of the OS for single processors to a unit of work which can be parallelized within the application controls security function with respect to a processing request from the unit of work in response to the processing request.
    Type: Application
    Filed: July 9, 2004
    Publication date: January 20, 2005
    Inventors: Hiroaki Inoue, Yoshiyuki Ito, Junji Sakai, Masato Edahiro
  • Publication number: 20040268171
    Abstract: In a parallel processing system by an OS for single processors which operates an OS and an existing application for single processors on a multiprocessor to realize parallel processing by the multiprocessor with respect to the application, a processor on a first processor side receives a request for activating or stopping a processor from a unit of work on any of the processors and controls a power supply management device of the OS for single processors to conduct activation or stop of the requested processor, while the processor requested to be activated or stop executes processing necessary for the activation or stop based on a notification from the first processor side.
    Type: Application
    Filed: May 26, 2004
    Publication date: December 30, 2004
    Applicant: NEC CORPORATION
    Inventors: Hiroaki Inoue, Yoshiyuki Ito, Junji Sakai, Masato Edahiro
  • Publication number: 20030212732
    Abstract: In the application parallel processing system, on specific one of processors forming a multi-processor, an application is operated independently of other processors and on other processors, a function expansion module is operated in parallel processing under control of the application. As a result, even in such a data processing device internally provided with a processor whose processing capacity is small as a portable terminal, applications can be operated smoothly.
    Type: Application
    Filed: April 24, 2003
    Publication date: November 13, 2003
    Applicant: NEC CORPORATION
    Inventors: Masato Edahiro, Junji Sakai, Tetsuya Minakami, Yoshiyuki Ito, Hiroaki Inoue
  • Publication number: 20030182355
    Abstract: The present invention relates to a parallel processing system by an OS for single processor capable of operating an OS for single processor and an existing application on a multiprocessor and achieving parallel processing by a multiprocessor with respect to the application, wherein the multiprocessor are logically divided into two groups, i.e., a first processor side and a second processor side, and units of work that are parallelizable within the application operating on the processors on the first processor side are controlled as new units of work on the processors on the second processor side.
    Type: Application
    Filed: March 19, 2003
    Publication date: September 25, 2003
    Applicant: NEC CORPORATION
    Inventors: Masato Edahiro, Yoshiyuki Ito, Junji Sakai, Tetsuya Minakami, Hiroaki Inoue
  • Patent number: 6239406
    Abstract: A laser beam machining apparatus has machining apparatus including a laser oscillator, a stage for moving a workpiece in XY directions, and a central processing unit (CPU) for controlling laser emission of the laser oscillator and movement of the stage. The CPU causes the laser beam machining apparatus to group machining points on the workpiece into a plurality of segments, each segment being a set of machining points aligned parallel to one of the X axis and Y axis, to create a shortest route through the plurality of segments, to drive the stage along the shortest route, and to apply a laser beam on the machining points on the shortest route.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: May 29, 2001
    Assignee: NEC Corporation
    Inventors: Yoshimi Onoma, Masato Edahiro
  • Patent number: 5944836
    Abstract: The invention provides a clock signal distributing circuit wherein the position at which the buffer section is disposed is determined from the positions and characteristics of the clock signal input section and the load section and the characteristics of the buffer section and the wiring section, and wirings are made through the clock signal input section, one or more stage buffer sections, and the load section, so that the signal transmission delay time as well as the skew of clock signals can be adjusted.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: August 31, 1999
    Assignee: NEC Corporation
    Inventor: Masato Edahiro