Abstract: A data holding circuit that retreats and restores internal statuses. The data holding portion includes a memory. At least one internal state of the data holding portion is retreated via a retreating signal line to the memory, while being restored via the memory through the restoration signal line.

Abstract: A data holding circuit that retreats and restore internal statuses. The data holding portion includes a memory. At least one internal state of the data holding portion is retreated via a retreating signal line to the memory, while being restored via the memory through the restoration signal line.

Abstract: A programmable logic LSI resolves a problem leaving some wiring resource extra upon realizing one circuit (some wiring cells are not used) and leaving some logical resource extra upon realizing another circuit (some logical cell are not used, and can realize both functions of logical resource and wiring resource with a single base cell. The base call for a programmable logic LSI which is formed by connecting a plurality of the base cells, includes a combined programmable circuit realizing a programmable logic circuit function and a programmable wiring circuit function, and a mode setting circuit for selectively making one of the programmable logic circuit function and the programmable wiring circuit function according to a mode information. Upon functioning as the programmable logic circuit, logical operation is performed with respect to an input signal input to the base cell to feed an output signal.

Abstract: In a multiple line buffer type memory LSI, when line buffers retaining data read out from a memory section does not exist in a multiple line buffer section, data retained in any of the line buffers are copied and held temporarily in standby in the write-back buffers. The data read out from the memory section are retained in the line buffers. The data temporarily held in standby in the write-back buffers are written back into the memory section.

Abstract: In a multiple line buffer type memory LSI, when line buffers retaining data read out from a memory section does not exist in a multiple line buffer section, data retained in any of the line buffers are copied and held temporarily in standby in the write-back buffers. The data read out from the memory section are retained in the line buffers. The data temporarily held in standby in the write-back buffers are written back into the memory section.

Abstract: Disclosed is a programmable device that has a programmable cell that operates as programmable logic or memory by internal storage means and a wiring network that is composed of a plurality of wiring lines and determines the line-connection state of a wiring group according to the storage means. In this device, the programmable cell is provided with n sets of input/output port groups, where n is an integer of 2 or more, and the wiring network is of m sets, where m is an integer of 2 or more.

Abstract: In a plural line buffer type memory LSI, a line selection register 16 (holding an address for designating a line buffer) is added. The value of the line selection register 16 is previously updated by a memory access instruction having a room in an address. Thus, it is possible to maintain compatibility with input/output terminals of a general purpose memory LSI, or to prevent the increase in the number of input/output terminals, and also to prevent the increase of the memory access delay attributable to the restriction in connection with the issue of the commands. Accordingly, it is possible to maintain the compatibility with the general purpose memory LSI having no line buffer, or alternatively to prevent the increase of the memory access delay attributable to a restriction in an interval for issuing the commands.

Abstract: In a line buffer type semiconductor memory device contructed by a memory section and a line buffer section including a plurality of line buffers each capable of storing data of one segment size, a direct fetch control section reads first data of one segment size from the memory section and writes the first data into one of the line buffers, and a direct restore control section reads second data of one segment size from one of the line buffers and writes the second data into the memory section.

Abstract: To decrease a number of cells for programmable wiring means in a programmable logic LSI. An element cell as programmable logic means in the programmable logic LSI comprises a memory circuit, a read-out circuit, and an inter-cell connection control circuit. The element cell unit functions also as programmable wiring means. Further, the input/output connections for a plurality of the element cells are assured by twisting inter-cell connection lines 108. Furthermore, a feed-back loop is formed by connecting input/output signal lines, when the element cell is operating as programmable logic means.

Abstract: A memory section and coprocessor sections in a coprocessor-integrated packet-type DRAM are provided with unique memory device ID and coprocessor device IDs respectively. The coprocessor-integrated packet-type DRAMs are connected to a single bus master type packet-type memory/coprocessor bus via external I/O terminals. A request packet is transmitted by the bus master to the packet-type memory/coprocessor bus, and each of the coprocessor-integrated packet-type DRAMs which received the request packet verifies a device ID field in the request packet against the memory device ID and the coprocessor device IDs stored in the coprocessor-integrated packet-type DRAM. If the device ID field matched, the request packet is decoded and memory access to the memory section or coprocessor access to the coprocessor section requested by the request packet is executed.

Abstract: To execute all processing in an array section of an array-type processor, each processor must execute processing of different types, i.e., processing of an operating unit and processing of a random logic circuit, which limits its size and processing performance. A data path section including processors arranged in an array are connected via programmable switches to primarily execute processing of operation and a state transition controller configured to easily implement a state transition function to control state transitions are independently disposed. These sections are configured in customized structure for respective processing purposes to efficiently implement and achieve the processing of operation and the control operation.

Abstract: The present invention provide a programmable device comprising: an array of plural programmable cells; a first sub-interconnection network comprising a plurality of first interconnections which extend to surround each of the plural programmable cells for transmitting data; and a second sub-interconnection network comprising a plurality of second interconnections which extend to surround each of the plural programmable cells for transmitting control informations, so that each of the plural programmable cells selects one of plural configuable informations stored therein in accordance with the control information supplied from the second sub-interconnection network.

Abstract: A memory large scale integrated circuit with a data compression/decompression function, applicable to a main memory system, graphics memory system and such is provided with a data compression/decompression section. In this structure, compressed data-read with respect to a memory section is performed with an application of a data compressor within the compression/decompression section, and compressed data-write with respect to the memory section is performed with an application of a data decompressor within the compression/decompression section. Owing to this structure, even when a data bandwidth is physically the same as in the conventional case, it is practically possible to achieve a larger data bandwidth in use.

Abstract: In order to achieve rapid reconfiguration of logic elements in a programmable logic device, a plurality of memory logic modules are arranged in a two-dimensional array. At least one logic element is provided in each of the plurality of memory logic modules. The logic element is provided with a configuration memory into which configuration data can be written to specify logic functions of the logic element. A memory element is provided in each of the plurality of memory logic modules. The memory element stores a plurality of configuration data with respect to the logic element, and one of the plurality of configuration data is written into the configuration memory of the logic element to configure or reconfigure the logic element.

Abstract: A multiple instruction parallel issue/execution management system including a forward map buffer for storing forward map information indicating whether or not the result value generated by execution of a given instruction is used an input operand in other instructions. The forward map buffer previously stores the forward map information for the result value, before the result value corresponding to the given instruction is actually generated, and when the result value corresponding to the given instruction is actually generated, the operands using the result value are specified by using the previously stored forward map information corresponding to the result value, and supplied to an instruction using the result value as an input operand.

Abstract: In a superscalar processor for fetching a prescribed peak number of instructions in parallel in each period until such instructions are fetched to a predetermined peak number, such as ten, an instruction parallel issue and execution administrating device comprises a forward map buffer for a forward map indicative of a result of each instruction for use as an operand by which one of other instructions of the predetermined peak number. The forward map is developed before the result is actually produced and is used, after the actual production, to indicate which one of such results should be used as the operand by the above-mentiond one of the other instructions.

Abstract: In a main memory with arithmetic logic processing capability, k first memories (k is an integer equal to or more than 0) are connected to a memory bus, for storing data. M second memories with arithmetic logic processing capability (m is an integer equal to or more than 1) are also connected to the memory bus. Each of the m second memories includes a memory section for storing data, and an arithmetic logic processing section. The arithmetic logic processing section performs a first processing to at least a part of the data stored in the memory section in response to a first instruction inputted via the memory bus, and allows a result of the first processing to be outputted onto the memory bus in response to a second instruction inputted via the memory bus. The arithmetic logic processing section may further includes a macro code RAM for storing macro codes.

Abstract: A parallel processor system executing a program consisted of a plurality of threads in parallel per threads, includes thread generating portion for managing three states of executing state, executable state and waiting state as states of the threads and generating other thread in the executable state by fork operation from the threads in the executing state on predetermined processor, thread execution control portion for making the first thread in the executable state to be executed on the processor, providing guarantee for data dependency between a plurality of first threads in the executing states on the processors, executing a second thread in the executable state in place of the first threads when the first thread in the executing state enters into waiting state with interrupting execution, and re-executing the first thread in the waiting state after termination of execution of the second thread.

Abstract: A multithreaded processor includes an instruction pipelined unit 140 and a register file 120 composed of a plurality of register banks 130. The register file 120 is coupled to an external memory 190 through register frame load/store lines 121, so that a register frame, which is defined as a content stored in one register bank 130, can be loaded and stored in bundle. When a thread parallel start instruction and a thread sequential start instruction are executed, the register frames are saved through the load/store lines 121. When a thread end instruction and a thread return instruction are executed, the register frames are restored through the load/store lines 121.

Abstract: A microprocessor 1 is coupled to a memory 2, and includes an instruction pipeline 3 and a register file 4. The register file 4 includes an address read/write circuit 5, a plurality of frame address storing registers 6 coupled to the address read/write circuit 5, data read/write circuits 7 and 10, and register banks 8 of the same number as that of the frame address storing registers 6. The register banks 8 is coupled to the data read/write circuits 7 and 10, and all the register banks 8 are composed of the same number of registers 9. The instruction pipeline 3 is coupled to the register file 4 through a register designating bus 104, a data transfer bus 105, and an address transfer bus 106. The instruction pipeline 3 is also coupled to the memory 2 through a memory address bus 101 and an instruction supply bus 102, and the data read/write circuit 10 is coupled to the memory 2 through a data transfer bus 103.