Abstract: An address generator generates a binary coded address signal consisting of a combination of bit-representative low swing complementary signals. The coded address signal is decoded by an address decoder in a concurrently amplifying manner to obtain a decoded address signal consisting of a combination of symbol-representative full swing signal pairs of logical signals. The decoder comprises a binary tree of sense amplifiers each serving for outputting a logical product of an input enable signal and a corresponding low swing complementary signal, so that a single logical signal has a high level at the output end of the decoder. The high level logical signal is employed to drive a word line for an access to an arbitrary location defined in a given memory or to a desired piece of data stored therein, at an address represented by the decoded address signal.

Abstract: A semiconductor static random access memory device has a bi-stable memory cell for storing a data bit in the form of potential difference between two memory nodes, and an equalizing transistor is connected between the two memory nodes for equalizing the two memory nodes at a balance level between a high level and a low level before rewriting the data bit, thereby causing the bi-stable memory cell to swing the voltage levels at the two memory nodes by a half of the potential difference.

Abstract: With addition/subtraction and product-sum operation procedures, a one-dimensional N-order discrete cosine transform (DCT) operation is performed so that N pieces of DCT results can be obtained from N pieces of original image data with arguments from 0 to (N-1). In the addition/subtraction procedure, among M pieces of data with arguments from 0 to (M-1) (M is a positive integer expressed as a positive power of 2 from 2 to N), two data for which the sum of the arguments is M-1 are subjected to addition/subtraction for (log.sub.2 N - 1) times to obtain M/2 pieces of addition results and subtraction results with arguments from 1 to (M/2-1). In the product-sum operation procedure, L pieces of data with arguments from 0 to (L-1) (L is a positive integer expressed as a positive power of 2 from 2 to N/2) and L.sup.2 pieces of DCT coefficients are subjected to product-sum operation for (log.sub.2 N - 1) times to obtain and output L pieces of DCT results.

Abstract: In an apparatus for adding first and second addresses to generate a third address and decoding the third address to generate a plurality of partial decoding signals, a plurality of partial decoding signal generating units, each for generating one of the partial decoding signals, are connected in parallel. Each of the partial decoding signal generating units includes an adder for adding a part of the first address to a part of the second address, a carry look ahead circuit, a decoder for decoding the output of the adder, and a shifter for shifting the partial decoding signal of the decoder. A carry output signal of one of the partial decoding signal generating units on the downstream side is supplied to the carry look ahead circuit and the shifter of another of the partial decoding signal generating units on the upstream side.

Abstract: A motion picture coder for coding plural macro blocks of motion picture data based on a standardizing system is disclosed. The coder comprises first and second pipe-lined processors executing different coding processes respectively, both of which are separated from one another so as to accomplish a parallel operation thereof. The first processor executes a motion vector detection for a second macro block, an inter-frame addition for a first macro block and an inter-frame difference for the first macro block. The second processor executes a discrete cosine transform for the first macro block, a quantization for the first macro block, an inverse quantization for the first macro block, an inverse discrete cosine transform for the first macro block and a loop filtering for the second macro block.

Abstract: A string collating system comprises an input device receiving a reference string and a string to be collated and for generating a coincidence signal when each constituent of the string to be collated is coincident to one character of the reference string, and a string comparator composed of cells arranged in M columns and in N rows (where M and N are integer), each cell f.sub.i,j (i=1 to M-1 and j=1 to N-1) being coupled to a rightward adjacent cell f.sub.i,j+1 through a first transfer circuit and also coupled to a downwardly adjacent cell f.sub.i+1,j through a second transfer circuit, each cell f.sub.i,j is further coupled to a rightward adjacent cell f.sub.i+1,j+1 through a third transfer circuit and also coupled to a rightward adjacent cell f.sub.i+1,j+1 through an automatic setting circuit, the cells in a first row being coupled to the input device so as to receive the coincidence signal, the first transfer circuit operating to transfer data stored in each cell f.sub.i,j to the cell f.sub.