Abstract: A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes selecting each word line through a row decoder connected to all word lines to switch all synaptic NVRAM cells of the selected lines. The method includes driving, on the selected lines, a wave generated by a PLL circuit connected to the row decoder. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines through a column decoder connected to all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.

Abstract: A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t1. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.

Abstract: A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes driving, on selected word lines from among the word lines, a wave generated by a PLL circuit. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.

Abstract: Described is a neuromorphic system implemented in hardware that implements neuron membrane potential update based on the leaky integrate and fire (LIF) model. The system further models synapse weights update based on the spike time-dependent plasticity (STDP) model. The system includes an artificial neural network in which the update scheme of neuron membrane potential and synapse weight are effectively defined and implemented.

Abstract: A computer-implemented method is provided for refreshing cells in a Non-Volatile Memory (NVM)-based neuromorphic circuit wherein synapses are each composed of a respective cell pair formed from a respective Gp cell and a respective Gm cell of the cells. The method includes randomly selecting multiple neurons and reading a conductance of any of the synapses connected to the multiple neurons. The method further includes selecting any of the synapses connected to the selected multiple neurons for which the Gm conductance has reached a maximum conductance. The method also includes resetting the Gp cell and Gm cell of the selected synapses, and setting, at most, one of the Gp cell and Gm cell of each of the selected synapses to recover an effective total weight of each of the selected synapses.

Abstract: An image processing apparatus is described comprising a first acquisition unit configured to acquire image data from an image capturing apparatus and a second acquisition unit configured to acquire display installation information indicating a configuration of one or more display screens in a display installation to be simulated. A generation unit is provided to generate, based on the display installation information and the acquired image data, a simulation image that simulates display of the image on the display installation. A display control unit is provided to display the simulation image on a display device.

Abstract: An electronic apparatus includes a housing, a substrate in the housing, components on the substrate, a reference temperature sensor, temperature sensors for the respective components, and an arithmetic processing unit. The arithmetic processing unit estimates an outside air temperature by using a reference temperature, temperatures acquired by the temperature sensors, first transfer functions, second transfer functions, and third transfer functions, and estimates a surface temperature of the housing based on the outside air temperature. Each first transfer function is defined based on a thermal resistance and a thermal time constant from a component to the reference temperature sensor. Each second transfer function is defined based on a thermal resistance and a thermal time constant from a component to an individual temperature sensor. Each third transfer function is defined based on a thermal resistance and a thermal time constant from a component to a surface of the housing.

Abstract: A method is provided of initializing a chip having synaptic NVRAM cells connected row-wise by word lines and column-wise by bit lines. The method includes driving, on selected word lines from among the word lines, a wave generated by a PLL circuit. The method includes generating standing waves from the wave on the selected lines by implementing a resonance detection point at an input end of each word line. The method includes applying a write voltage on all bit lines. The method includes simultaneously driving each of the synaptic NVRAM cells of the selected lines by different writing currents for different durations in order to set different analog values to the synaptic NVRAM cells.

Abstract: A thermoelectric generator includes a perovskite dielectric substrate containing Sr and Ti and having electric conductivity by being doped to n-type; an energy filter formed on a top surface of the perovskite dielectric substrate, the energy filter including a first perovskite dielectric film, which contains Sr and Ti, has electric conductivity by being doped to n-type, and has a conduction band at an energy level higher than that of the perovskite dielectric substrate; a first electrode formed in electrical contact with a bottom surface of the perovskite dielectric substrate; and a second electrode formed in electrical contact with a top surface of the energy filter. The thermoelectric generator produces a voltage between the first and second electrodes by the top surface of the energy filter being exposed to a first temperature and the bottom surface of the perovskite dielectric substrate being exposed to a second temperature.

Abstract: A neuromorphic circuit, chip, and method are provided. The neuromorphic circuit includes a crossbar synaptic array cell. The crossbar synaptic array cell includes a Complimentary Metal-Oxide-Semiconductor (CMOS) transistor having an on-resistance controlled by a gate voltage of the CMOS transistor to update a weight of the crossbar synaptic array cell. The neuromorphic circuit further includes a set of row-lines respectively connecting the synaptic array cell in series to a plurality of pre-synaptic neurons at first ends thereof. The neuromorphic circuit also includes a set of column-lines respectively connecting the synaptic array cell in series to a plurality of post-synaptic neurons at second ends thereof. The gate voltage of the CMOS transistor is controlled by performing a charge sharing technique that updates the weight of the crossbar synaptic array cell using non-overlapping pulses on control lines that are aligned with the set of row lines and the set of column lines.

Abstract: Described is a neuromorphic system implemented in hardware that implements neuron membrane potential update based on the leaky integrate and fire (LIF) model. The system further models synapse weights update based on the spike time-dependent plasticity (STDP) model. The system includes an artificial neural network in which the update scheme of neuron membrane potential and synapse weight are effectively defined and implemented.

Abstract: A computer-implemented method is provided for refreshing cells in a Non-Volatile Memory (NVM)-based neuromorphic circuit wherein synapses are each composed of a respective cell pair formed from a respective Gp cell and a respective Gm cell of the cells. The method includes randomly selecting multiple neurons and reading a Gp conductance and a Gm conductance of any of the synapses connected to the multiple neurons. The method further includes selecting any of the synapses connected to the selected multiple neurons for which any of the Gp conductance or the Gm conductance have reached a maximum conductance. The method also includes resetting the Gp cell and Gm cell of the selected synapses, and setting, at most, one of the Gp cell and Gm cell of each of the selected synapses to recover an effective total weight of each of the selected synapses.

Abstract: A memory cell structure includes a plurality of write lines arranged for writing a synapse state to a synapse memory cell including a plurality of cell components each including at least one unit cell, each of the plurality of write lines being used for writing the synapse state by writing a first set of states to a corresponding cell component of the plurality of cell components by writing one of a second set of states to each unit cell included in the corresponding cell component, and the first set depending on the second set.

Abstract: A thermoelectric generator includes a perovskite dielectric substrate containing Sr and Ti and having electric conductivity by being doped to n-type; an energy filter formed on a top surface of the perovskite dielectric substrate, the energy filter including a first perovskite dielectric film, which contains Sr and Ti, has electric conductivity by being doped to n-type, and has a conduction band at an energy level higher than that of the perovskite dielectric substrate; a first electrode formed in electrical contact with a bottom surface of the perovskite dielectric substrate; and a second electrode formed in electrical contact with a top surface of the energy filter. The thermoelectric generator produces a voltage between the first and second electrodes by the top surface of the energy filter being exposed to a first temperature and the bottom surface of the perovskite dielectric substrate being exposed to a second temperature.

Abstract: A thermoelectric conversion element includes a film composed of a conductive oxide, a first electrode disposed on one end of the film composed of the conductive oxide, and a second electrode disposed on another end of the film composed of the conductive oxide, wherein the conductive oxide has a tetragonal crystal structure expressed by ABO3-x, where 0.1<x<1, wherein the conductive oxide has a band structure in which a Fermi level intersects seven bands between a ? point and an R point, and wherein the first electrode and the second electrode are disposed on the film composed of the conductive oxide so that electrical charge moves in a direction of a smallest vector among three primitive translation vectors of the crystal structure.

Abstract: An electronic apparatus includes a housing; a substrate disposed on the inner side of the housing; a plurality of temperature sensors disposed on the substrate; and a processor. The processor performs a procedure including calculating heat source temperatures of a plurality of heat sources disposed on the substrate from temperatures measured by the temperature sensors by using a first heat transfer model not including a first parameter representing a transient response of heat transfer from the heat sources to the temperature sensors; and calculating a surface temperature of a surface of the housing from the heat source temperatures by using a second heat transfer model including the first parameter and a second parameter representing a transient response of heat transfer from the heat sources to the surface.

Abstract: An image processing apparatus includes a first acquisition unit configured to acquire an imaging angle of view at which an input image is captured, a second acquisition unit configured to acquire display system information indicating, in a display system including a display portion, a display angle, which is a visual angle at which the display portion is viewed from a viewpoint position, and a generation unit configured to, using a correspondence relationship between a projection plane and the display portion in a virtual space based on the imaging angle of view and the display system information, generate a display image to be displayed on the display portion.

Abstract: An image processing apparatus is configured to generate a display image to be produced on a display system including a display unit. The image processing apparatus includes an acquisition unit configured to acquire orientation information indicating an orientation of an imaging apparatus when the imaging apparatus captures an input image, a setting unit configured to set a projection plane in a virtual space based on the orientation information, and a generation unit configured to generate the display image to be produced on the display unit with use of a relationship between the input image and the projection plane.

Abstract: A neuromorphic chip includes synaptic cells including respective resistive devices, axon lines, dendrite lines and switches. The synaptic cells are connected to the axon lines and dendrite lines to form a crossbar array. The axon lines are configured to receive input data and to supply the input data to the synaptic cells. The dendrite lines are configured to receive output data and to supply the output data via one or more respective output lines. A given one of the switches is configured to connect an input terminal to one or more input lines and to changeably connect its one or more output terminals to a given one or more axon lines.

Abstract: A synapse memory system includes: synapse memory cells provided at cross points of axon lines and dendrite lines, each synapse memory cell being associated with nonvolatile random-access memory (NVRAM), each synapse memory cell being configured to store a weight value according to an output level of a write signal; a write portion configured to write the weight value to each synapse memory cell, the write portion including a write driver and an output controller, the write driver being a digital driver configured to output the write signal to a subject synapse memory cell, the output controller being configured to control the output level of the write signal of the write driver; and read drivers configured to read the weight value stored in the synapse memory cells.