Abstract: The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device in which a chip area is not increased, manufacturing costs are suppressed, and an image averaging processing can be carried out. Pixel regions Pmn are arranged in a matrix form in regions defined by horizontal selection lines RWm and vertical selection lines CLn. Each of the pixel regions Pmn includes a photodiode 10, a source follower amplifier 14 for converting an electric charge of the photodiode 10 into a voltage and amplifying it to output image data, and a horizontal selection transistor 16 for outputting the image data to a predetermined one of the vertical selection lines CLn. An amplifier/noise cancel circuit 6 has a built-in image averaging circuit for carrying out an averaging processing of the image data outputted from at least two of the plurality of the pixel regions Pmn.

Abstract: A CMOS image sensor that reduces kTC noise in a wide band. A pixel circuit corresponding to one pixel includes a photoelectric conversion element for carrying out the photoelectric conversion of incident light, a reset transistor for resetting a cathode of the photoelectric conversion element to initial voltage, an amplifying transistor for converting electric charges accumulated in the photoelectric conversion element to voltage, and a row selection transistor for selecting signals output from pixel areas arranged in a row direction. A voltage control circuit controls the potential of a gate of the reset transistor during a period when the photoelectric conversion element is reset to change ON-state resistance of the reset transistor. By doing so, a cutoff frequency for a low-pass filter formed in the pixel circuit by ON-state resistance of the reset transistor and parasitic capacitance produced at the cathode on the photoelectric conversion element will be controlled.

Abstract: A DC-DC converter that suppresses increase in area and obtains high conversion efficiency irrespective of the output current. A controller controls a first output transistor and a second output transistor in a PWM operation mode or a linear operation mode based on output voltage of the DC-DC converter. The controller operates the DC-DC converter as a switching regulator that activates and inactivates the first output transistor and the second output transistor in a complementary manner during the PWM operation mode. The controller operates the DC-DC converter as a linear regulator that inactivates the second output transistor and controls the ON-resistance value of the first output transistor to perform linear operation with the first output transistor during the linear operation mode.

Abstract: The CMOS sensor circuit comprises a photodiode, a reset transistor resetting the photodiode to an initial voltage, and a voltage control circuit controlling a gate potential of the reset transistor to a potential other than power source potentials. The voltage control circuit consists of an inverter circuit driving a gate of the reset transistor. The inverter circuit includes a P-channel MOS transistor, an N-channel MOS transistor, and a transistor inserted between a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor so as to control a blooming.

Abstract: An image sensor for capturing image, has: a plurality of pixels arranged in a matrix each including a photoelectric conversion element for generating current according to received light intensity and a reset transistor for resetting a node of the photoelectric conversion element to a reset potential; and a sample hold circuit for sample holding a pixel potential according to the potential of the node of the pixel. And the sample hold circuit outputs the differential potential, between a first pixel potential at an end of the integration period after a first reset operation of the pixel and a second pixel potential at an end of a reset noise read period after a second reset operation after the integration period, as a pixel signal. Also in the sample hold circuit, when the second pixel potential during the reset noise read period exceeds a predetermined threshold level, the second pixel potential is set to a predetermined reference potential.

Abstract: A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.

Abstract: An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

Abstract: A low-power CMOS image sensor that gets distinct images in which interference does not occur between adjacent pixels without changing an element in a circuit. Each of pixel circuits arranged like a matrix converts incident light into electrical signals with a photoelectric conversion element. Image signals output from pixel circuits adjacent to each other in a horizontal direction are input to a signal processing circuit in each column, undergo predetermined signal processing, and are switched and output in order by a horizontal scanning circuit. The signal processing circuits are arranged and each of fixed potential wirings parallel to one another is located between adjacent signal processing circuits. Therefore, adjacent signal processing circuits are electrically shielded by a fixed potential wiring.

Abstract: A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.

Abstract: An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

Abstract: A correlated double sampling circuit that reduces a shift in the potential of a node on the reference voltage side produced by reset operation. A reset signal RST is turned to “H” and then is turned to “L.” By doing so, a photodiode begins integration according to the intensity of light. This detected signal is sent to a CDS circuit. An SW1 and a connection switch for sampling in the CDS circuit are turned to ON to accumulate the detected signal according to integration time in C1 and C2 as electric charges. After a certain period of time elapsed, the SW1 and connection switch for sampling are turned to OFF to hold the detected signal sampled. Next, the RST is turned again to “H” and the SW1 is turned to ON. Then the RST is turned to “L” and the SW1 is turned to OFF. By doing so, reset noise is sampled and held in the C1. As a result, only a signal component can be extracted from the detected signal.

Abstract: A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.

Abstract: A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.

Abstract: The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device which has a small element size and a wide opening ratio, and can reduce a kTC noise. A photodiode 10, a reset transistor 12, a source follower amplifier 14, and a horizontal selection transistor 16 are formed in each of pixel regions Pmn. A kTC noise reduction circuit 6VR1 for reducing a kTC noise and a CDS circuit 6CL1 are formed outside of the pixel regions Pmn. A differential amplifier is constituted by a first differential transistor 62 of the kTC noise reduction circuit 6VR1 and the source follower amplifier 14 in each of the pixel regions Pmn.

Abstract: An operational amplifier capable of offset cancel in a shorter period, as well as a line driver capable of shortening one horizontal period and a liquid crystal display device are provided. In the operational amplifier of the invention, a time necessary for feed back control can be shortened than usual by a constitution that an output voltage VO in one horizontal period H1 which is one horizontal period before is defined as a reference voltage in an offset cancel preparatory period HC2, thereby changing the output voltage VO(2) only by the offset voltage VO(2) by the feed back control. In the line driver of the invention, the operational amplifier not used for the output of display data D1 to D6 conducts offset cancel operation and it is successively shifted on every one horizontal period. Since it is no more necessary to incorporate the offset cancel preparatory period in the output period, one horizontal period can be shortened further.

Abstract: Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.

Abstract: Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.

Abstract: In a data driver 10A of a dot-inversion driving type, the outputs of voltage buffer amplifiers B1 to B12 are connected to respective data bus lines D1 to D12 of a LCD panel, short-circuiting switches S1, S3, S5, S7, S9 and S11 are connected between ones of every other adjacent data bus lines concerned with the same display color, and interconnecting lines on first and second rows are arranged in a staggered configuration. These short-circuiting switches are formed at one sides of every other data bus lines, and turned on by a control circuit 13 when the outputs of the voltage buffer amplifier are in a high impedance state.

Abstract: An image sensor for capturing image, has: a plurality of pixels arranged in a matrix each including a photoelectric conversion element for generating current according to received light intensity and a reset transistor for resetting a node of the photoelectric conversion element to a reset potential; and a sample hold circuit for sample holding a pixel potential according to the potential of the node of the pixel. And the sample hold circuit outputs the differential potential, between a first pixel potential at an end of the integration period after a first reset operation of the pixel and a second pixel potential at an end of a reset noise read period after a second reset operation after the integration period, as a pixel signal. Also in the sample hold circuit, when the second pixel potential during the reset noise read period exceeds a predetermined threshold level, the second pixel potential is set to a predetermined reference potential.

Abstract: An image processing circuit for a color image sensor, comprising a color sensitivity correction circuit which adds/subtracts a predetermined offset to/from pixel signals being output by amplifying photoelectric conversion signals of pixels, which have photoelectric conversion element and are arranged in column and row directions, for each column, and multiplies the result by a predetermined gain, wherein the predetermined offset includes a first offset, which is set according to each color, and a second offset, which is set according to a plurality of columns. According to the present invention, the offset of the color sensitivity correction circuit includes a first offset, which is set according to each color, and a second offset, which is set according to a plurality of columns, therefore, periodic moiré in the vertical direction, which is caused by the column output circuit and the output signal supply circuit for each column, can be suppressed, and image quality can be improved.