Abstract: A selector circuit comprises four 2-input selectors 50 to 53 each selecting in response to the complementary selection signals D2 and *D2 of MSB and a 4-input selector 24A selecting in response to complementary selection signals D1, *D1, D0 and *D0 of the lower 2 bit. In each of the 2-input selectors 50 to 53, one ends of two switching transistors are commonly connected to each other and the two switching transistors are adjacently arranged in the same row. In the 4-input selector 24A, 4 analogue switch circuits, each of which has two switching transistors arranged in the same row and serially connected, are arranged in parallel to one another and each is arranged in the same row as that of a corresponding 2-input selector. Same selectors are arranged in a row on a substrate and trunk lines for providing two families of gradation potentials V0 to V7 to the circuits are laid above the circuits. Upper/lower trunk line pairs are in the third and second wiring layer, respectively.

Abstract: A selector circuit, for selecting and outputting, in accordance with N-bit input data, one gray level reference voltage from 2N gray level reference voltages, comprises: a plurality of select transistor arrays, which are provided in parallel between terminals of the gray level reference voltages and an output terminal and which have a plurality of serially connected transistors that are drive-controlled by the input data, wherein the select transistor arrays are each commonly provided for a group of M (M is a plurality and M<2N) gray level reference voltages among the 2N gray level reference voltages and are made to assume a drive enabled state by means of time division in correspondence with the M gray level reference voltages.

Abstract: A low-power CMOS image sensor that gets distinct images in which interference does not occur between adjacent pixels without changing an element in a circuit. Each of pixel circuits arranged like a matrix converts incident light into electrical signals with a photoelectric conversion element. Image signals output from pixel circuits adjacent to each other in a horizontal direction are input to a signal processing circuit in each column, undergo predetermined signal processing, and are switched and output in order by a horizontal scanning circuit. The signal processing circuits are arranged and each of fixed potential wirings parallel to one another is located between adjacent signal processing circuits. Therefore, adjacent signal processing circuits are electrically shielded by a fixed potential wiring.

Abstract: A correlated double sampling circuit that reduces a shift in the potential of a node on the reference voltage side produced by reset operation. A reset signal RST is turned to “H” and then is turned to “L.” By doing so, a photodiode begins integration according to the intensity of light. This detected signal is sent to a CDS circuit. An SW1 and a connection switch for sampling in the CDS circuit are turned to ON to accumulate the detected signal according to integration time in C1 and C2 as electric charges. After a certain period of time elapsed, the SW1 and connection switch for sampling are turned to OFF to hold the detected signal sampled. Next, the RST is turned again to “H” and the SW1 is turned to ON. Then the RST is turned to “L” and the SW1 is turned to OFF. By doing so, reset noise is sampled and held in the C1. As a result, only a signal component can be extracted from the detected signal.

Abstract: A CMOS image sensor that reduces kTC noise in a wide band. A pixel circuit corresponding to one pixel includes a photoelectric conversion element for carrying out the photoelectric conversion of incident light, a reset transistor for resetting a cathode of the photoelectric conversion element to initial voltage, an amplifying transistor for converting electric charges accumulated in the photoelectric conversion element to voltage, and a row selection transistor for selecting signals output from pixel areas arranged in a row direction. A voltage control circuit controls the potential of a gate of the reset transistor during a period when the photoelectric conversion element is reset to change ON-state resistance of the reset transistor. By doing so, a cutoff frequency for a low-pass filter formed in the pixel circuit by ON-state resistance of the reset transistor and parasitic capacitance produced at the cathode on the photoelectric conversion element will be controlled.

Abstract: An operational amplifier, which generates an output voltage at an output terminal that is equal to an input voltage, comprises: a differential circuit, which compares the input voltage and the output voltage; first and second output transistors, which are controlled by the output of the differential circuit to drive the output terminal; and an offset cancel circuit, connected with the differential circuit, for storing an offset amount of this differential circuit, wherein, in the offset cancel period in which the offset amount is stored by the offset cancel circuit, the output terminal is driven by the second output transistor, and in the operational amplifier operation period following the offset cancel period, the output terminal is driven by the first output transistor.

Abstract: A differential amplifying circuit 11 includes a current mirror circuit having first and second current ends to which drains of MOS transistors M8 and M9 are respectively connected, and a pair of differential MOS transistors M1 and M2 having gates between which a switch SW1 is connected. A reference potential Vref is applied to the gate of the MOS transistors M9. A switch SW2 is connected between the output VO of an output buffer circuit 12 and the gate of a MOS transistor M1, and a switch SW3 is connected between the output VO and the gate of the MOS transistor M8. During the offset-cancel preparation period, the switches SW1 and SW3 are on and the switch SW2 is off. Next, the switches SW1 to SW3 are turned over, consequently outputting offset-canceled potential VO.

Abstract: A semiconductor device carries out a test utilizing contact with a probe needle without being affected by narrowing of the pitch at which output pads are arranged. The device is equipped with test circuits provided between a plurality of output buffers via which signals are output and output pads corresponding thereto. The test circuit includes output switches caused to sequentially make connections by a controller in test and interpad switches involved in making connections of the output pads with a test pad by the controller in test. In test, probe needles are brought into contact with the test pad. The output pads are not used in test, and can be arranged at a narrowed pitch. Thus, the chip area can be reduced and are therefore so that the pitch for the output pads can be narrowed and the chip area can be decreased.

Abstract: A selector circuit comprises four 2-input selectors 50 to 53 each selecting in response to the complementary selection signals D2 and *D2 of MSB and a 4-input selector 24A selecting in response to complementary selection signals D1, *D1, D0 and *D0 of the lower 2 bit. In each of the 2-input selectors 50 to 53, one ends of two switching transistors are commonly connected to each other and the two switching transistors are adjacently arranged in the same row. In the 4-input selector 24A, 4 analogue switch circuits, each of which has two switching transistors arranged in the same row and serially connected, are arranged in parallel to one another and each is arranged in the same row as that of a corresponding 2-input selector. Same selectors are arranged in a row on a substrate and trunk lines for providing two families of gradation potentials V0 to V7 to the circuits are laid above the circuits. Upper/lower trunk line pairs are in the third and second wiring layer, respectively.

Abstract: An operational amplifier, which generates an output voltage at an output terminal that is equal to an input voltage, comprises: a differential circuit, which compares the input voltage and the output voltage; first and second output transistors, which are controlled by the output of the differential circuit to drive the output terminal; and an offset cancel circuit, connected with the differential circuit, for storing an offset amount of this differential circuit, wherein, in the offset cancel period in which the offset amount is stored by the offset cancel circuit, the output terminal is driven by the second output transistor, and in the operational amplifier operation period following the offset cancel period, the output terminal is driven by the first output transistor.

Abstract: The CMOS sensor circuit comprises a photodiode, a reset transistor resetting the photodiode to an initial voltage, and a voltage control circuit controlling a gate potential of the reset transistor to a potential other than power source potentials. The voltage control circuit consists of an inverter circuit driving a gate of the reset transistor. The inverter circuit includes a P-channel MOS transistor, an N-channel MOS transistor, and a transistor inserted between a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor so as to control a blooming.

Abstract: The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device in which a chip area is not increased, manufacturing costs are suppressed, and an image averaging processing can be carried out. Pixel regions Pmn are arranged in a matrix form in regions defined by horizontal selection lines RWm and vertical selection lines CLn. Each of the pixel regions Pmn includes a photodiode 10, a source follower amplifier 14 for converting an electric charge of the photodiode 10 into a voltage and amplifying it to output image data, and a horizontal selection transistor 16 for outputting the image data to a predetermined one of the vertical selection lines CLn. An amplifier/noise cancel circuit 6 has a built-in image averaging circuit for carrying out an averaging processing of the image data outputted from at least two of the plurality of the pixel regions Pmn.

Abstract: The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device which has a small element size and a wide opening ratio, and can reduce a kTC noise. A photodiode 10, a reset transistor 12, a source follower amplifier 14, and a horizontal selection transistor 16 are formed in each of pixel regions Pmn. A kTC noise reduction circuit 6VR1 for reducing a kTC noise and a CDS circuit 6CL1 are formed outside of the pixel regions Pmn. A differential amplifier is constituted by a first differential transistor 62 of the kTC noise reduction circuit 6VR1 and the source follower amplifier 14 in each of the pixel regions Pmn.

Abstract: An offset cancel circuit for an operational amplifier comprises a capacitive element for storing a voltage to be amplified by an operational amplifier section and containing an offset, and for feedback-controlling a voltage value of the operational amplifier section based on the stored voltage, and switching elements for switching operation between the storage of the voltage in the capacitive element and the feedback control based on the value of the voltage stored in the capacitive element. The capacitive element and the switching elements can be used to cancel accurately an offset in the operational amplifier section without increasing the gate areas of transistors in the operational amplifier section.

Abstract: In a data driver 10A of a dot-inversion driving type, the outputs of voltage buffer amplifiers B1 to B12 are connected to respective data bus lines D1 to D12 of a LCD panel, short-circuiting switches S1, S3, S5, S7, S9 and S11 are connected between ones of every other adjacent data bus lines concerned with the same display color, and interconnecting lines on first and second rows are arranged in a staggered configuration. These short-circuiting switches are formed at one sides of every other data bus lines, and turned on by a control circuit 13 when the outputs of the voltage buffer amplifier are in a high impedance state.

Abstract: An offset cancel circuit for an operational amplifier comprises a capacitive element for storing a voltage to be amplified by an operational amplifier section and containing an offset, and for feedback-controlling a voltage value of the operational amplifier section based on the stored voltage, and switching elements for switching operation between the storage of the voltage in the capacitive element and the feedback control based on the value of the voltage stored in the capacitive element. The capacitive element and the switching elements can be used to cancel accurately an offset in the operational amplifier section without increasing the gate areas of transistors in the operational amplifier section.

Abstract: A liquid crystal display panel includes a driver having pairs of first and second D/A converters, corresponding pairs of first and second polarity changeover switches, and plural switching elements. Each of the first D/A converters receives a picture signal and outputs a positive-polarity voltage and each of the second D/A converters receives the picture signal and outputs a negative-polarity voltage. The first polarity changeover switches are connected to the outputs of the first and second D/A converters and alternately output the positive and negative polarity voltages. The second polarity changeover switches are also connected to the outputs of the first and second D/A converters and output a reverse polarity voltages. The switching elements are connected between the outputs of the first D/A converters and the first polarity switch and the output of the second D/A converters and the second polarity changeover switch.

Abstract: Lower level of data latch holding a digital image data and a positive selector arranged immediately above positive gradation voltage line, for selecting positive analog gradation voltage of positive gradation levels are take as a set, and upper level of data latch holding a digital image data and a negative selector arranged immediately above negative gradation voltage line, for selecting negative analog gradation voltage of negative gradation levels are take as a set. Two sets are arranged in alignment in vertical direction. A plurality of sets of vertically aligned sets are arranged horizontally to shorten a length in horizontal direction with respect to gradation voltage lines.

Abstract: A voltage selector for a D/A converter compensates for varying output response times for different value input signals due to variations in signal line lengths. The voltage selector includes a plurality of first stage transfer gates, including first and second groups of transfer gates, and a plurality of second stage transfer gates, including a first transfer gate connected to the first group of transfer gates and a second transfer gate connected to the second group of transfer gates. The number of the first group of transfer gates is greater than the number of the second group of transfer gates and the number of the second group of transfer gates is set such that a load of the second transfer gate is smaller than a load of the first transfer gate.