Patents by Inventor Masayasu Komyo
Masayasu Komyo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140119142Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.Type: ApplicationFiled: January 6, 2014Publication date: May 1, 2014Applicant: Renesas Electronics CorporationInventors: Masayasu KOMYO, Yoichi IIZUKA
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Publication number: 20140062595Abstract: A highly reliable circuit is realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.Type: ApplicationFiled: August 21, 2013Publication date: March 6, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masafumi MITSUISHI, Masayasu KOMYO, Souji SUNAIRI
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Patent number: 8653851Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.Type: GrantFiled: June 29, 2011Date of Patent: February 18, 2014Assignee: Renesas Electronics CorporationInventors: Masayasu Komyo, Yoichi Iizuka
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Publication number: 20140016401Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.Type: ApplicationFiled: September 19, 2013Publication date: January 16, 2014Applicant: Renesas Electronics CorporationInventors: Masayasu Komyo, Yoichi Iizuka
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Publication number: 20130343144Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.Type: ApplicationFiled: August 29, 2013Publication date: December 26, 2013Inventors: Masayasu KOMYO, Yoichi IIZUKA
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Patent number: 8558572Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.Type: GrantFiled: October 12, 2011Date of Patent: October 15, 2013Assignee: Renesas Electronics CorporationInventors: Masayasu Komyo, Yoichi Iizuka
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Patent number: 8552758Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.Type: GrantFiled: May 14, 2012Date of Patent: October 8, 2013Assignee: Renesas Electronics CorporationInventors: Masayasu Komyo, Yoichi Iizuka
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Publication number: 20120223769Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.Type: ApplicationFiled: May 14, 2012Publication date: September 6, 2012Inventors: Masayasu KOMYO, Yoichi IIzuka
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Patent number: 8253436Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.Type: GrantFiled: September 7, 2010Date of Patent: August 28, 2012Assignee: Renesas Electronics CorporationInventors: Masayasu Komyo, Yoichi Iizuka
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Publication number: 20120026812Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.Type: ApplicationFiled: October 12, 2011Publication date: February 2, 2012Inventors: Masayasu KOMYO, Yoichi Iizuka
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Patent number: 8102186Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.Type: GrantFiled: September 7, 2010Date of Patent: January 24, 2012Assignee: Renesas Electronics CorporationInventors: Masayasu Komyo, Yoichi Iizuka
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Publication number: 20110255354Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Inventors: Masayasu KOMYO, Yoichi IIZUKA
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Patent number: 7999572Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.Type: GrantFiled: September 7, 2010Date of Patent: August 16, 2011Assignee: Renesas Electronics CorporationInventors: Masayasu Komyo, Yoichi Iizuka
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Patent number: 7956638Abstract: An impedance adjusting circuit that includes an external terminal to which an external resistor is connected, a first transistor array of a first conductivity type that is connected in parallel between the external terminal and a first power supply terminal and changes a voltage of the external terminal by adjusting an impedance in response to a first control signal, a second transistor array of a second conductivity type that is connected in parallel between the external terminal and a second power supply terminal and changes the voltage of the external terminal by adjusting the impedance in response to a second control signal, and a control circuit that specifies the first control signal according to a comparison result between the voltage of the external terminal and a reference voltage and specifies the second control signal in a different period from a period to specify the first control signal.Type: GrantFiled: January 4, 2010Date of Patent: June 7, 2011Assignee: Renesas Electronics CorporationInventors: Yoichi Iizuka, Masayasu Komyo
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Publication number: 20110057720Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.Type: ApplicationFiled: September 7, 2010Publication date: March 10, 2011Inventors: Masayasu KOMYO, Yoichi IIZUKA
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Publication number: 20110057722Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.Type: ApplicationFiled: September 7, 2010Publication date: March 10, 2011Inventors: Masayasu KOMYO, Yoichi Iizuka
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Publication number: 20110057721Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.Type: ApplicationFiled: September 7, 2010Publication date: March 10, 2011Inventors: Masayasu KOMYO, Yoichi IIZUKA
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Publication number: 20100188116Abstract: An impedance adjusting circuit that includes an external terminal to which an external resistor is connected, a first transistor array of a first conductivity type that is connected in parallel between the external terminal and a first power supply terminal and changes a voltage of the external terminal by adjusting an impedance in response to a first control signal, a second transistor array of a second conductivity type that is connected in parallel between the external terminal and a second power supply terminal and changes the voltage of the external terminal by adjusting the impedance in response to a second control signal, and a control circuit that specifies the first control signal according to a comparison result between the voltage of the external terminal and a reference voltage and specifies the second control signal in a different period from a period to specify the first control signal.Type: ApplicationFiled: January 4, 2010Publication date: July 29, 2010Inventors: Yoichi IIZUKA, Masayasu Komyo
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Patent number: 7180326Abstract: A noise elimination circuit sets a certain time period for eliminating noise occurring immediately after a change in the logic level of an input signal by a delay time of a first delay buffer. It also adjusts the timing of switching by delay times of second and third delay buffers. The noise elimination circuit thereby blocks the input signal for a certain period of time immediately after the change in the logic level of the input signal to keep a switching signal by a latch circuit or transmit only the same logic level as the input signal to an output.Type: GrantFiled: November 30, 2004Date of Patent: February 20, 2007Assignee: NEC Electronics CorporationInventor: Masayasu Komyo
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Publication number: 20050122129Abstract: A noise elimination circuit sets a certain time period for eliminating noise occurring immediately after a change in the logic level of an input signal by a delay time of a first delay buffer. It also adjusts the timing of switching by delay times of second and third delay buffers. The noise elimination circuit thereby blocks the input signal for a certain period of time immediately after the change in the logic level of the input signal to keep a switching signal by a latch circuit or transmit only the same logic level as the input signal to an output.Type: ApplicationFiled: November 30, 2004Publication date: June 9, 2005Applicant: NEC Electronics CorporationInventor: Masayasu Komyo