Abstract: The invention provides a communication semiconductor integrated circuit device (RF IC) capable of pulling in the frequency of a PLL circuit to a desired set frequency at high speed even in the case where a frequency settable range of the PLL circuit is wide without providing a current source other than a current source for charging and discharging in an normal operation. An oscillator as a component of a PLL circuit is constructed so as to be operative in a plurality of bands. In a state where a control voltage of the oscillator is fixed to a predetermined value, an oscillation frequency of the oscillator is measured in each of bands and stored in a storing circuit. A set value for designating a band supplied at the time of PLL operation is compared with the stored measured frequency value. From a result of comparison, a band to be actually used in the oscillator is determined, and a frequency difference between the maximum frequency of the selected band and the set frequency is obtained.

Abstract: An input/output pin for test corresponding to a test circuit of the digital section is used in common as the input/output pin for usual operation of the analog section, the selection switches are respectively provided between the relevant analog pin and analog circuit and on a signal line up to the test circuit of the digital section from the relevant analog pin and the switches are provided at both end portions of the signal line between the test circuit of digital section and the input/output pin for common use in order to fix the voltage of the signal line to the predetermined voltage such as the ground voltage during the usual operation.

Abstract: An input/output pin for test corresponding to a test circuit of the digital section is used in common as the input/output pin for usual operation of the analog section, the selection switches are respectively provided between the relevant analog pin and analog circuit and on a signal line up to the test circuit of the digital section from the relevant analog pin and the switches are provided at both end portions of the signal line between the test circuit of digital section and the input/output pin for common use in order to fix the voltage of the signal line to the predetermined voltage such as the ground voltage during the usual operation.

Abstract: An image input system includes a solid state image pickup device and a preprocessor for performing correlated double sampling amplification on an output of the image pickup device and outputting a video signal. The preprocessor has a correlated double sampling amplifier for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the image pickup device and a signal level in a charge signal output period; and an offset cancelling circuit for cancelling an offset voltage corresponding to the difference voltage in a state where the image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other, so that circuits following the correlated double sampling amplifier are not influenced by the offset voltage.

Abstract: An image input system comprises a solid state image pickup device and a preprocessor (3) for performing correlated double sampling amplification on an output signal of the solid state image pickup device and outputting a video signal. The preprocessor comprises: a correlated double sampling amplifier (30) for outputting signal information corresponding to a difference voltage between the black level in a feedthrough period of the solid state image pickup device and a signal level in a charge signal output period; and offset cancelling means (38) for applying an offset cancelling voltage for cancelling an offset voltage corresponding to the difference voltage between the black level and the signal level in a state where the solid state image pickup device is optically interrupted to the input terminal of the correlated double sampling amplifier. The correlated double sampling amplifier cancels out the offset voltage and the offset cancelling voltage as signal components of polarities opposite to each other.

Abstract: A wireless communication system, which is provided with a PLL circuit having a plurality of oscillators and is capable of processing two or more transmit and receive signal different in frequency band from one another according to the switching between the oscillators, has a reset means which resets a voltage applied to each of filter capacitors lying within the PLL circuit to a predetermined voltage when the switching between the oscillators is performed.

Abstract: Into an internal circuit to operate in a high-frequency band, there is incorporated a protective circuit of a multistage connection which is constructed to include a plurality of diode-connected transistors having a low parasitic capacity and free from a malfunction even when an input signal higher than the power supply voltage is applied. Into an internal circuit to operate in a low-frequency band, there is incorporated a protective circuit which is constructed to include one diode-connected transistor. The protective circuits include two lines of protective circuit, in which the directions of electric currents are so reversed as to protect the internal circuits against positive/negative static electricities.

Abstract: A flash A/D converter includes a plurality of master comparators for comparing a plurality of reference voltages and an input analog signal to absorb a current with a constant value from a non-inverted output or inverted output of each master comparator, a plurality of constant current sources, a plurality of load resistors and a plurality of slave comparators for outputting desired digital signals. The constant current value of one of the constant current sources coupled to a signal line coupled to the input of the slave comparator of a lower bit side is set to a value larger than that of one of the constant current sources coupled to a signal line coupled to the input of the slave comparator of a higher bit side. Thereby, it is possible to provide a flash A/D converter which has a low power consumption and a high speed.

Abstract: An analog-to-digital converter receiving an analog signal and producing a digital output signal corresponding to a value of the analog signal includes a plurality of sets each having a plurality of sample-and-hold circuits having inputs connected in parallel with each other, an analog switch responsive to a control signal to apply the input analog signal to the junction of the parallel connection of the plurality of sample-and-hold circuits, and a plurality of encoders respectively connected to outputs of the plurality of sets to convert output signals of the plurality of sample-and-hold circuits into a binary signal. Each of the plurality of sample-and-hold circuits includes a series connection of a second analog switch and a capacitor and the analog-to-digital converter further includes comparators connected to outputs of the plurality of sample-and-hold circuits. Advantageously, errors in timing for sampling conducted in the plurality of sample-and-hold circuits can be eliminated.

Abstract: A resistor is provided with a plurality of turn parts whose corners have an obtuse flexional angle in order to improve the relative resistance precision. A ladder resistor can be formed with a plurality of such resistors connected in series, and various electronic devices are formed employing the ladder resistor.