Abstract: Techniques for transmitting SONET/SDH traffic over an Advanced Switching compatible switch fabric. In one implementation, SONET/SDH traffic may be aggregated and encapsulated into Advanced Switching compatible packets. In one implementation, the contents of the Advanced Switching compatible packets may be configurable and directions on how to unpack the Advanced Switching compatible packets may be transmitted to end point nodes. In one implementation, SONET/SDH pointer justification generation may be divided between a source node which transmits SONET/SDH traffic to the switch fabric and an end point node which receives SONET/SDH traffic from the switch fabric.

Abstract: A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.

Abstract: Methods and apparatus relating to distribution of intelligence across a network are described. In one embodiment, one or more content processors may be provided at the edge of a computer network (e.g., prior to a point where data is aggregated or routed by the network). Other embodiments are also disclosed.

Abstract: Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.

Abstract: A method is used to authenticate a wireless device for secure operation on a wireless local area network, the wireless local area network including a controller. The method to include broadcasting from the controller a configuration message based on the controller being physically switched to a configuration mode. The method to also include accepting at the controller a response from the wireless device, the response accepted based on receiving the response within a fixed time period following the broadcasting of the configuration message, the accepted response including information encrypted using the controller's public key. A user message is obtained, the user message entered by the user at the controller and maintained at the controller. The wireless device is authenticated based on whether the response including the encrypted information, when decrypted with a private key associated with the controller's public key, matches the user message.

Abstract: Techniques for transmitting SONET/SDH traffic over an Advanced Switching compatible switch fabric. In one implementation, SONET/SDH traffic may be aggregated and encapsulated into Advanced Switching compatible packets. In one implementation, the contents of the Advanced Switching compatible packets may be configurable and directions on how to unpack the Advanced Switching compatible packets may be transmitted to end point nodes. In one implementation, SONET/SDH pointer justification generation may be divided between a source node which transmits SONET/SDH traffic to the switch fabric and an end point node which receives SONET/SDH traffic from the switch fabric.

Abstract: A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.

Abstract: Techniques for processing traffic for transmission over an Advanced Switching compatible switch fabric.

Abstract: A method of compiling code includes assigning an endian type to data. An endian flip operation is performed based on the endian type of the data and a target system. Other embodiments are described and claimed.

Abstract: A scalable, high-performance interconnect scheme for a multi-threaded, multi-processing system-on-a-chip network processor unit. An apparatus implementing the technique includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and a chassis interconnect that may be controlled to selectively connects a given master to a given target. In one embodiment, the chassis interconnect comprises a plurality of sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus, a pull data bus for target writes, and a push data bus for target reads. Multiplexer circuitry for each of the command bus, pull data bus, and push data bus is employed to selectively connect a given cluster to a given target to enable commands and data to be passed between the given cluster and the given target.

Abstract: Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.

Abstract: Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store.

Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

Abstract: An apparatus and method for performing two-pass real time video compression is provided. Tactical decisions such as encoding and quantization values are determined in software, whereas functional execution steps are performed in hardware. By appropriately apportioning the tasks between software and hardware, the benefits of each type of processing are exploited, while minimizing both hardware complexity and data transfer requirements. One key concept that allows the compression unit to operate in real time is that the architecture and pipelining both allow for B frames to be executed out of order. By buffering B frames, two-pass motion estimation techniques can be performed to tailor bit usage to the requirements of the frame, and therefore provide a more appealing output image.

Abstract: A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: An architecture to perform a hash algorithm. Embodiments of the invention relate to the use of processor architecture logic to implement an addition operation of initial state information to intermediate state information as required by hash algorithms while reducing the contribution of the addition operation to the critical path of the algorithm's performance within the processor architecture.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: Method and apparatus for performing centralized cyclic redundancy checks (CRC). For one embodiment a current thread of execution compares a connection index with that of a previous thread of execution. If they share the same connection index, a CRC calculation may be performed without providing a CRC residue to a centralized CRC unit since the most recently produced CRC residue by would be associated with a preceding sequential cell of the same packet. For an alternative embodiment a current thread of execution requests a CRC calculation and provides a connection index to the centralized CRC unit, which is used to access a content addressable memory (CAM). A hit in the CAM indicates that the CRC unit may use the CRC residue associated with the connection index in the CAM since it would have resulted from a preceding sequential cell.