Abstract: A method of communicating between a first and a second processor includes the first processor sending a datum over a common control bus, and the second processor receiving the datum from the common control bus.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: A router includes a communications bus, a second bus, and at least two processors. The second bus transfers ready status data from ports connected to the communications bus. The processors are connected to the communications and second busses. One of the processors controls the communications bus at each time. Each processor transfers control of the communications bus to another processor in response to receiving a request for control from the other processor.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: An integrated circuit includes a random access memory (RAM) storage and a controller both located on one semiconductor chip. The controller is coupled to read data from and write data to the RAM storage. The controller is programmable to perform bitwise operations on data words stored in the RAM.

Abstract: A method for decompressing compressed data elements, drawing that decompression operation, the intermediate coefficients are organized in a matrix configuration such that the number of transpose operations are minimized. The organization of that matrix includes storing sequential coefficients, translated from the compressed data, in sequential locations of sequential columns of the matrix. The transpose operation is performed during the inverse discrete cosine operation portion of the decompression operation.

Abstract: In accordance with the present invention, a method and apparatus are provided for efficiently transmitting data between stages of a decompression pipeline by implementing a control store register for minimizing the amount of data that is transferred among decompression units. The control store register is a register having memory locations that are associated with decompressed coefficients. As the coefficients are decompressed, a determination is made as to whether they contain zero or non-zero values. The result of that determination is stored in the control store register such that the processor performing the inverse quantization and inverse discrete cosine operations only retrieves non-zero coefficients. Therefore, data transmission is performed in an efficient manner.

Abstract: A method and apparatus performs high speed forward or reverse Discrete Cosine Transform (DCT) for video compression and decompression that is optimized in both directions and which uses minimal hardware. This invention can be used to improve the speed of electronic transmission of images, decrease the electronic bandwidth necessary to transmit images electronically, increase the density of electronic storage of images, and speed up image enhancement operations.