Abstract: A method of manufacture of an optical waveguide structure including the steps of: providing a multilayer semiconductor wafer including a III-V semiconductor substrate, a III-V semiconductor top layer and an etch stop layer sandwiched therebetween, the etch stop layer including aluminium and phosphorous; and etching through the top layer to the etch stop layer by use of a dry etch containing chlorine to provide two spaced apart recesses defining the optical waveguide therebetween.

Abstract: A reflecting light emitting structure includes a substrate having a plurality of grooves formed in a first face of the substrate is disclosed. The first face is in a first crystallographic plane. Each of the plurality of grooves includes a first sidewall that is coplanar with a second crystallographic plane and a second sidewall that is coplanar with a third crystallographic plane. A buffer layer is provided on the substrate to reduce mechanical strain between the substrate and a light emitting diode (LED) fabricated on the buffer layer.

Abstract: A heterojunction bipolar transistor comprising a substrate; a collector on the substrate; a base layer on the collector; an emitter layer on the base layer; the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and base; the collector, base and emitter layers being npn or pnp doped respectively; characterized in that the lower emitter layer has a larger bandgap than the base layer and is AlxIn1-xP or GaxAl1-xP, x being in the range 0+ to 1.

Abstract: An optical waveguide structure including a III-V semiconductor substrate, a III-V semiconductor top layer, and an etch stop layer sandwiched therebetween, the etch stop layer containing aluminium and phosphorous, the top layer including first and second spaced apart recesses extending through the top layer to the etch stop layer and defining an optical waveguide therebetween. Also a method of manufacture of an optical waveguide structure including the steps of: providing a multilayer semiconductor wafer including a III-V semiconductor substrate, a III-V semiconductor top layer and an etch stop layer sandwiched therebetween, the etch stop layer including aluminium and phosphorous; and etching through the top layer to the etch stop layer by use of a dry etch containing chlorine to provide two spaced apart recesses defining the optical waveguide therebetween.

Abstract: A reflecting light emitting structure includes a substrate having a plurality of grooves formed in a first face of the substrate is disclosed. The first face is in a first crystallographic plane. Each of the plurality of grooves includes a first sidewall that is coplanar with a second crystallographic plane and a second sidewall that is coplanar with a third crystallographic plane. A buffer layer is provided on the substrate to reduce mechanical strain between the substrate and a light emitting diode (LED) fabricated on the buffer layer.

Abstract: A light emitting structure having reverse voltage protection (RVP) is provided along with disclosure of a method for fabricating the light emitting structure. The light emitting structure includes a substrate having a first face, a second face, and a p-n junction formed within the substrate between a p-type layer and an n-type layer, wherein the p-type layer and the n-type layer are adapted as a RVP diode. A buffer layer is provided on the substrate, and a light emitting diode (LED) is fabricated on the buffer layer. The LED is then electrically coupled to the RVP diode in an anti-parallel diode pair (APDP) configuration.

Abstract: A III-V field effect transistor comprising a semiconductor channel layer having an electrically conducting channel; an ohmic contact layer on the semiconductor channel layer, the ohmic contact layer having a recess structure disposed therethrough to the semiconductor channel layer; the bottom of the ohmic contact layer comprising an etch stop layer comprising Aluminium and Phosphorous and defining the shape of the recess at its junction with the semiconductor channel layer.

Abstract: A III-V field effect transistor comprising a semiconductor channel layer having an electrically conducting channel; an ohmic contact layer on the semiconductor channel layer, the ohmic contact layer having a recess structure disposed therethrough to the semiconductor channel layer; the bottom of the ohmic contact layer comprising an etch stop layer comprising Aluminium and Phosphorous and defining the shape of the recess at its junction with the semiconductor channel layer.

Abstract: A III-V field effect transistor includes a semiconductor channel layer having an electrically conducting channel and an ohmic contact layer on the semiconductor channel layer. The ohmic contact layer has a recess structure disposed therethrough to the semiconductor channel layer. The bottom of the ohmic contact layer includes an etch stop layer including Aluminum and Phosphorous and defining the shape of the recess at its junction with the semiconductor channel layer.

Abstract: A heterojunction bipolar transistor comprising a substrate; a collector on the substrate; a base layer on the collector; an emitter layer on the base layer; the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and base; the collector, base and emitter layers being npn or pnp doped respectively; characterised in that the lower emitter layer has a larger bandgap than the base layer and is AlxIn1-xP or GaxAl1-xP, x being in the range 0+ to 1.

Abstract: A III-V field effect transistor comprising a semiconductor channel layer having an electrically conducting channel; an ohmic contact layer on the semiconductor channel layer, the ohmic contact layer having a recess structure disposed therethrough to the semiconductor channel layer; the bottom of the ohmic contact layer comprising an etch stop layer comprising Aluminium and Phosphorous and defining the shape of the recess at its junction with the semiconductor channel layer.

Abstract: An electrically conducting track comprising an electrically conducting track layer; a semiconductor substrate; and a dielectric layer sandwiched between track layer and semiconductor substrate; the electrically conducting track further comprising an electrically conducting resistor track between semiconductor substrate and dielectric layer

Abstract: A method of handling a semiconductor wafer from which a plurality of semiconductor devices are to be fabricated during a semiconductor device fabrication process. The method includes the steps of attaching a flexible connected layer to a semiconductor wafer layer mounted on a carrier substrate and separating the wafer layer from the carrier substrate while supported by the flexible connected layer.

Abstract: A method of handling a semiconductor wafer from which a plurality of semiconductor devices are to be fabricated during a semiconductor device fabrication process. The method includes the steps of attaching a flexible connected layer to a semiconductor wafer layer mounted on a carrier substrate and separating the wafer layer from the carrier substrate while supported by the flexible connected layer.

Abstract: The present invention relates to a heterojunction bipolar transistor structure having a device mesa 401 with a collector region 402, a base region 403 and an emitter region 404. An emitter metal layer 405 is connected to a ballast resistor 406 which in turn is connected to an emitter bump 407 by way of the air bridge 408. The thermal bump 409 is connected to the emitter metallization by way of a layer of heat dissipation material 410, preferably silicon nitride. The present structure enables dissipation of heat at the emitter contact as well as a ballast resistor connected to the emitter by way of metallization 405. This arrangement enables the dissipation of joule heat to avoid higher temperature of operation which results increased current at the collector which increases the temperature thereby further increasing the current, as well as provides a ballast resistor to reduce the collector current back to an acceptable value to avoid thermal runaway.