Patents by Inventor Matthias Lipinski
Matthias Lipinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8697339Abstract: Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece.Type: GrantFiled: April 6, 2011Date of Patent: April 15, 2014Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., Infineon Technologies AGInventors: Haoren Zhuang, Chong Kwang Chang, Alois Gutmann, Jingyu Lian, Matthias Lipinski, Len Yuan Tsou, Helen Wang
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Patent number: 8394574Abstract: Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask.Type: GrantFiled: September 27, 2011Date of Patent: March 12, 2013Assignee: Infineon Technologies AGInventors: Chandrasekhar Sarma, Jingyu Lian, Matthias Lipinski, Haoren Zhuang
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Patent number: 8349528Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.Type: GrantFiled: June 20, 2011Date of Patent: January 8, 2013Assignee: Infineon Technologies AGInventors: Matthias Lipinski, Alois Gutmann, Jingyu Lian, Chandrasekhar Sarma, Haoren Zhuang
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Publication number: 20120013884Abstract: Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask.Type: ApplicationFiled: September 27, 2011Publication date: January 19, 2012Applicant: Infineon Technologies AGInventors: Chandrasekhar Sarma, Jingyu Lian, Matthias Lipinski, Haoren Zhuang
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Patent number: 8071261Abstract: Lithography masks and methods of manufacture thereof are disclosed. For example, a method of manufacturing a lithography mask includes forming a stack over a substrate. The stack includes bottom attenuated phase shift material layers, intermediate opaque material layers, and finally top resist layers. The method further includes patterning the stack and then trimming the resist layers to uncover a portion of the opaque material layers. The uncovered opaque material layers are subsequently etched followed by removal of any remaining resist layers.Type: GrantFiled: July 20, 2007Date of Patent: December 6, 2011Assignee: Infineon Technologies AGInventors: Alois Gutmann, Sajan Marokkey, Henning Haffner, Chandrasekhar Sarma, Haoren Zhuang, Matthias Lipinski
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Patent number: 8067135Abstract: Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask.Type: GrantFiled: July 23, 2010Date of Patent: November 29, 2011Assignee: Infineon Technologies AGInventors: Chandrasekhar Sarma, Jingyu Lian, Matthias Lipinski, Haoren Zhuang
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Patent number: 8063406Abstract: Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.Type: GrantFiled: October 22, 2010Date of Patent: November 22, 2011Assignee: Infineon Technologies AGInventors: Haoren Zhuang, Matthias Lipinski, Jingyu Lian, Chandrasekhar Sarma
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Publication number: 20110250530Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.Type: ApplicationFiled: June 20, 2011Publication date: October 13, 2011Applicant: Infineon Technologies AGInventors: Matthias Lipinski, Alois Gutmann, Jingyu Lian, Chandrasekhar Sarma, Haoren Zhuang
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Patent number: 8007985Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.Type: GrantFiled: January 30, 2006Date of Patent: August 30, 2011Assignee: Infineon Technologies AGInventors: Matthias Lipinski, Alois Gutmann, Jingyu Lian, Chandrasekhar Sarma, Haoren Zhuang
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Publication number: 20110183266Abstract: Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. A polymer material is disposed over the masking material. The masking material and the polymer layer are used to pattern the material layer of the workpiece.Type: ApplicationFiled: April 6, 2011Publication date: July 28, 2011Inventors: Haoren Zhuang, Chong Kwang Chang, Alois Gutmann, Jingyu Lian, Matthias Lipinski, Len Yuan Tsou, Helen Wang
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Patent number: 7892939Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.Type: GrantFiled: March 6, 2008Date of Patent: February 22, 2011Assignee: Infineon Technologies AGInventors: Roland Hampp, Manfred Eller, Jin-Ping Han, Matthias Lipinski
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Publication number: 20110031563Abstract: Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.Type: ApplicationFiled: October 22, 2010Publication date: February 10, 2011Applicant: INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: Haoren Zhuang, Matthias Lipinski, Jingyu Lian, Chandrasekhar Sarma
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Patent number: 7842579Abstract: Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.Type: GrantFiled: January 22, 2007Date of Patent: November 30, 2010Assignee: Infineon Technologies AGInventors: Haoren Zhuang, Matthias Lipinski, Jingyu Lian, Chandrasekhar Sarma
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Publication number: 20100283052Abstract: Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask.Type: ApplicationFiled: July 23, 2010Publication date: November 11, 2010Inventors: Chandrasekhar Sarma, Jingyu Lian, Matthias Lipinski, Haoren Zhuang
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Patent number: 7794903Abstract: Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask.Type: GrantFiled: August 15, 2006Date of Patent: September 14, 2010Assignee: Infineon Technologies AGInventors: Chandrasekhar Sarma, Jingyu Lian, Matthias Lipinski, Haoren Zhuang
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Publication number: 20100120177Abstract: A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.Type: ApplicationFiled: January 21, 2010Publication date: May 13, 2010Applicant: INFINEON TECHNOLOGIES AGInventors: Haoren Zhuang, Alois Gutmann, Matthias Lipinski, Chandrasekhar Sarma, Jingyu Lian
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Patent number: 7674350Abstract: A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.Type: GrantFiled: January 22, 2007Date of Patent: March 9, 2010Assignee: Infineon Technologies AGInventors: Haoren Zhuang, Alois Gutmann, Matthias Lipinski, Chandrasekhar Sarma, Jingyu Lian
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Publication number: 20090227086Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.Type: ApplicationFiled: March 6, 2008Publication date: September 10, 2009Inventors: Roland Hampp, Manfred Eller, Jin-Ping Han, Matthias Lipinski
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Patent number: 7541234Abstract: Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.Type: GrantFiled: November 3, 2005Date of Patent: June 2, 2009Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing Ltd., Infineon Technologies AGInventors: Chong Kwang Chang, Haoren Zhuang, Matthias Lipinski, Shailendra Mishra, O Sung Kwon, Tjin Tjin Tjoa, Young Gun Ko
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Publication number: 20090023078Abstract: Lithography masks and methods of manufacture thereof are disclosed. For example, a method of manufacturing a lithography mask includes forming a stack over a substrate. The stack includes bottom attenuated phase shift material layers, intermediate opaque material layers, and finally top resist layers. The method further includes patterning the stack and then trimming the resist layers to uncover a portion of the opaque material layers. The uncovered opaque material layers are subsequently etched followed by removal of any remaining resist layers.Type: ApplicationFiled: July 20, 2007Publication date: January 22, 2009Inventors: Alois Gutmann, Sajan Marokkey, Henning Haffner, Chandrasekhar Sarma, Haoren Zhuang, Matthias Lipinski