Abstract: Methods for manufacturing semiconductor devices are disclosed. One preferred embodiment is a method of processing a semiconductor device. The method includes providing a workpiece having a material layer to be patterned disposed thereon. A masking material is formed over the material layer of the workpiece. The masking material includes a lower portion and an upper portion disposed over the lower portion. The upper portion of the masking material is patterned with a first pattern. An additional substance is introduced and the lower portion of the masking material is patterned. The masking material and the additional substance are used to pattern the material layer of the workpiece.

Abstract: Methods of forming integrated circuit devices include steps to selectively widen portions of a mask pattern extending adjacent an outer edge of a semiconductor wafer. These steps to selectively widen portions of the mask pattern are performed so that more uniform center-to-edge critical dimensions (CD) can be achieved when the mask pattern is used to support photolithographically patterning of underlying layers (e.g., insulating layers, antireflective coatings, etc.).

Abstract: A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter.

Abstract: Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.

Abstract: Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is provided, and a layer of photosensitive material of the first semiconductor device is patterned with a plurality of corner rounding test features using the mask and a lithography process. An amount of corner rounding of the lithography process is measured by analyzing the plurality of corner rounding test features relative to other of the plurality of corner rounding test features formed on the layer of photosensitive material of the semiconductor device. The lithography process or the mask is altered in response to the amount of corner rounding measured, and a second semiconductor device is provided. The second semiconductor device is affected using the altered lithography process or the altered mask.

Abstract: Process control systems and methods for semiconductor device manufacturing are disclosed. A plurality of feedback and feed-forward loops are used to accurately control the critical dimension (CD) of features formed on material layers of semiconductor devices. Semiconductor devices with features having substantially the same dimension for each die across the surface of a wafer may be fabricated using the novel process control systems and methods described herein.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.

Abstract: A process for generating a hard mask for the patterning of a first layer includes applying a second layer, which includes carbon, to the first layer that is to be patterned. A third layer, which includes silicon and carbon, is spun onto the second layer and an organic antireflection coating layer that is to be used with an overlying photoresist layer patternable using 193 nm technology, is appllied to the spun-on third layer.

Abstract: Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.

Abstract: Plasma encapsulation for electronic and microelectronic components such as OLEDs. The invention relates to a plasma encapsulation for electronic and microelectronic components such as OLEDs. However, a conventional standard plasma coating process is not used; instead, an especially gentle plasma coating process which does not cause any damage to sensitive components such as an OLED is used, such as the pulsed method or the “remote” or “after glow method.

Abstract: A process for generating a hard mask for the patterning of a first layer includes applying a second layer, which includes carbon, to the first layer that is to be patterned. A third layer, which includes silicon and carbon, is spun onto the second layer and an organic antireflection coating layer is applied to the spun-on third layer.

Abstract: A process of using a-C:H layer as a hardmask material with tunable etch resistivity in a RIE process that alleviates the addition of a layer forming gas to the etchant when making a semiconductor device, comprising: a) providing a semiconductor substrate; b) forming a hardmask of amorphous carbon-hydrogen (a-C:H) layer by plasma enhancement over the semiconductor substrate; c) forming an opening in the hardmask layer to form an exposed surface portion of the hardmask layer; and d) etching the exposed surface portion of the hardmask layer without the addition of a layer forming gas using RIE to form a trench feature with sufficient masking and side wall protection.

Abstract: Disclosed is a method of tungsten-based hard mask etching of a wafer, comprising providing a patterned tungsten-based hard mask atop a metal-based surface of said wafer, etching through said pattern with a plasma etch that is selective for said metal-based surface with respect to tungsten, and executing a flash etch selective for tungsten, said etch of at least a minimum duration effective in removing substantially all defects caused by tungsten particulate contaminating said wafer. In another aspect of the first embodiment, said tungsten-based hard mask comprises a material selected from tungsten or an alloy thereof. In another aspect of the first embodiment, said metal based surface comprises a material selected from aluminum or an alloy thereof.

Abstract: A method and a system for performing a metal reactive ion etching (RIE) process is disclosed. The metal RIE process comprises at least three steps: a metal RIE step, a stripping step and a wet cleaning step. The metal RIE step and the stripping step are carried out in a main reactive chamber.

Abstract: The invention relates to a plasma encapsulation for electronic and microelectronic components such as OLEDs. However, a conventional standard plasma coating process is not used; instead, an especially gentle plasma coating process which does not cause any damage to sensitive components such as an OLED is used, such as the pulsed method or the “remote” or “after glow method.

Abstract: A process of using a-C:H layer as a hardmask material with tunable etch resistivity in a RIE process that alleviates the addition of a layer forming gas to the etchant when making a semiconductor device, comprising:

Abstract: Discharging the reaction water from the novel PEM fuel cells does not require humidification of the reaction gases or an increase in the gas pressure. This is attained in that a hydrophobic layer on the cathode side is used which has a smaller pore size than the layer on the anode side. The reaction water is removed via the anode during the operation of the fuel cell.

Abstract: Disclosed is a method of tungsten-based hard mask etching of a wafer, comprising providing a patterned tungsten-based hard mask atop a metal-based surface of said wafer, etching through said pattern with a plasma etch that is selective for said metal-based surface with respect to tungsten, and executing a flash etch selective for tungsten, said etch of at least a minimum duration effective in removing substantially all defects caused by tungsten particulate contaminating said wafer.

Abstract: A thin, flat, and porous carbon gas diffusion electrode having a side in contact with a supply of gas and a side in contact with an electrolyte, comprises a pyrolysis product of a composite of an organic aerogel or xerogel and a reinforcing skeleton consisting at least in part of organic material. The porosity of the carbon gas diffusion electrode according to the invention can be regulated at will while the surface of the electrode is smooth.

Abstract: A gas diffusion electrode made of carbon, a process for producing an electrode and a carbonizable composite are provided. Thin, flat, porous gas diffusion electrodes made of carbon, which have a smooth surface and in which the porosity can be regulated at will, are obtained by pyrolysis of a composite of an organic polymer having a spatial globular structure (SGS polymer) and a reinforcing skeleton formed at least in part of organic material.